Ranking Routes In Semiconductor Wafer Fabs

We develop a method to estimate the quality of processing routes in a wafer fabrication process. Ranking such routes can be useful for identifying the “best” and “worst” routes when making adjustments to recipes. Route categorization is also useful in developing efficient scheduling algorithms. In particular, we propose a method for ranking routes based on count-based metrics such as the number of defects on a wafer. We start with a statistical model to produce a “local” ranking of a tool and then build a “global” ranking via a heuristic procedure. Creating a fully statistical procedure for ranking routes in semiconductor fabrication plants is virtually impossible, given the number of possible routes and the limited data available. Nonetheless, our discussions with working engineers indicate that even approximate rankings are useful for making better operational decisions.

Nanoscale wafer patterning using SPM induced local anodic oxidation in InP substrates

Scanning probe microscopy assisted local anodic oxidation offers advantages over other semiconductor fabrication techniques as it is a low contamination method. We demonstrate the fabrication of deep and highly reproducible nanohole arrays on InP using local anodic oxidation. Nanohole and nano-oxide mound radius and depth are controlled independently by altering atomic force microscope tip bias and humidity, with a maximum nanohole depth of 15.6 ± 1.2 nm being achieved. Additionally, the effect of tip write speed on oxide line formation is compared for n-type, p-type and semi-insulating substrates, which shows that n-type InP oxidises at a slower rate that semi-insulated or p-type InP. Finally, we calculate the activation energy for LAO of semi-insulating InP to be 0.4 eV, suggesting the oxidation mechanism is similar to that which occurs during plasma oxidation.

A Hybrid Approach Combining Fuzzy c-Means-Based Genetic Algorithm and Machine Learning for Predicting Job Cycle Times for Semiconductor Manufacturing

Job cycle time is the cycle time of a job or the time required to complete a job. Prediction of job cycle time is a critical task for a semiconductor fabrication factory. A predictive model must forecast job cycle time to pursue sustainable development, meet customer requirements, and promote downstream operations. To effectively predict job cycle time in semiconductor fabrication factories, we propose an effective hybrid approach combining the fuzzy c-means (FCM)-based genetic algorithm (GA) and a backpropagation network (BPN) to predict job cycle time. All job records are divided into two datasets: the first dataset is for clustering and training, and the other is for testing. An FCM-based GA classification method is developed to pre-classify the first dataset of job records into several clusters. The classification results are then fed into a BPN predictor. The BPN predictor can predict the cycle time and compare it with the second dataset. Finally, we present a case study using the actual dataset obtained from a semiconductor fabrication factory to demonstrate the effectiveness and efficiency of the proposed approach.

Super-Resolution Optical Microscopy for Investigations of Defects in Semiconductor Device

Ripples scattering of sidewall in pattern devices is efficient and necessary for monitoring the semiconductor fabrication process. As a step towards improving the imaging quality in terms of scattering, an attempt has been made to use our recently reported method called Parametric Indirect Microscopic Imaging (PIMI) for the thin layer of pattern devices. The present study demonstrates that the resolving power of PIMI imaging for the sidewall of the pattern devices is better than that of the conventional microscopy techniques. The better resolving power of the present PIMI technique for imaging the sidewalls paves the (new) way for its industrial application for the inspection of the integrated semiconductor circuits. For the demonstration, PIMI images have been compared with AFM, which are very close agreement.

An MDP-Based Lifter Assignment Algorithm for Inter-Line Transportation in Semiconductor Fabrication

As semiconductor device geometries continue to shrink, the semiconductor manufacturing process becomes increasingly complex. This usually results in unbalanced utilization of machines and decreases overall productivity. One way to resolve such a problem is to share the resource capacity between different lines divided by floors. To this end, designing an efficient lifter assignment method to more efficiently manage transfer requests (TRs) of wafer lots to different floors is required. Motivated by this, our study addresses the assignment of lifters for delivering wafer lots to different floors. Unlike previous studies, which consider the current state of the system, our study considers both the current and possible future states of the system. We formulate an optimization model based on the Markov decision process. Then, we design an efficient method as a solution using both clustering and tournament selection methods. Experiments based on historical data confirm the effectiveness of the proposed algorithm in reducing travel times and delivery delays compared to the benchmark rules in practice. Sensitivity analysis demonstrates the robustness of the proposed model as the number of TRs increased. The proposed approach is expected to yield significant economic savings in both operating costs and labor.

A Review of the Progress of Thin-Film Transistors and Their Technologies for Flexible Electronics

Flexible electronics enable various technologies to be integrated into daily life and fuel the quests to develop revolutionary applications, such as artificial skins, intelligent textiles, e-skin patches, and on-skin displays. Mechanical characteristics, including the total thickness and the bending radius, are of paramount importance for physically flexible electronics. However, the limitation regarding semiconductor fabrication challenges the mechanical flexibility of thin-film electronics. Thin-Film Transistors (TFTs) are a key component in thin-film electronics that restrict the flexibility of thin-film systems. Here, we provide a brief overview of the trends of the last three decades in the physical flexibility of various semiconducting technologies, including amorphous-silicon, polycrystalline silicon, oxides, carbon nanotubes, and organics. The study demonstrates the trends of the mechanical properties, including the total thickness and the bending radius, and provides a vision for the future of flexible TFTs.