pipeline adc Latest Research Papers

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3137342 ◽

2022 ◽

pp. 1-1

Author(s):

Yanbo Zhang ◽

Jin Zhang ◽

Shubin Liu ◽

Ruixue Ding ◽

Yan Zhu ◽

...

Keyword(s):

Noise Shaping ◽

Pipeline Adc

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A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm

10.1109/icta53157.2021.9661855 ◽

2021 ◽

Author(s):

Liran Dong ◽

Yujun Shu ◽

Yongzhen Chen ◽

Jiangfeng Wu

Keyword(s):

Digital Filter ◽

Continuous Time ◽

Pipeline Adc

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Design of an 8-bit Pipeline ADC using Flash and Delay Line Architecture

2021 2nd International Conference for Emerging Technology (INCET) ◽

10.1109/incet51464.2021.9456420 ◽

2021 ◽

Author(s):

N Bharathesh patel ◽

Manju Devi

Keyword(s):

Delay Line ◽

Pipeline Adc

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A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431444 ◽

2021 ◽

Author(s):

Yanbo Zhang ◽

Jin Zhang ◽

Shubin Liu ◽

Zhangming Zhu ◽

Yan Zhu ◽

...

Keyword(s):

Noise Shaping ◽

Pipeline Adc ◽

Over Time

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A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-021-01814-1 ◽

2021 ◽

Author(s):

Hsin-Shu Chen ◽

Chien-Jian Tseng ◽

Cheng-Ming Chen ◽

Hsiang-Wen Chen

Keyword(s):

Pipeline Adc

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27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9365833 ◽

2021 ◽

Author(s):

Hongshuai Zhang ◽

Yan Zhu ◽

Chi-Hang Chan ◽

R. P. Martins

Keyword(s):

Error Tolerance ◽

Noise Shaping ◽

Pipeline Adc ◽

Gain Error

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A 65 nm CMOS Continuous-Time Pipeline ADC achieving 70 dB SNDR in 100 MHz Bandwidth

IEEE Solid-State Circuits Letters ◽

10.1109/lssc.2021.3071965 ◽

2021 ◽

pp. 1-1

Author(s):

Saravana Manivannan ◽

Shanthi Pavan

Keyword(s):

Continuous Time ◽

Pipeline Adc

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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3111912 ◽

2021 ◽

pp. 1-1

Author(s):

Hongshuai Zhang ◽

Yan Zhu ◽

Chi-Hang Chan ◽

Rui P. Martins

Keyword(s):

Error Tolerance ◽

Noise Shaping ◽

Pipeline Adc ◽

Gain Error

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A High Linearity T&H circuit for 1GHz Pipeline ADC in 65nm CMOS

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278027 ◽

2020 ◽

Author(s):

H. J. Wu ◽

Y. P. Zeng ◽

X. L. Xing ◽

N. Lin ◽

Q. Li

Keyword(s):

Pipeline Adc ◽

High Linearity

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A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2020.3006149 ◽

2020 ◽

Vol 67 (11) ◽

pp. 3618-3629

Author(s):

Chulhyun Park ◽

Tao Chen ◽

Kyoohyun Noh ◽

Dadian Zhou ◽

Suraj Prakash ◽

...

Keyword(s):

Pipeline Adc

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pipeline adc
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations

A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm

Design of an 8-bit Pipeline ADC using Flash and Delay Line Architecture

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration

A 65 nm CMOS Continuous-Time Pipeline ADC achieving 70 dB SNDR in 100 MHz Bandwidth

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration

A High Linearity T&H circuit for 1GHz Pipeline ADC in 65nm CMOS

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier

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pipeline adcRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations

A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm

Design of an 8-bit Pipeline ADC using Flash and Delay Line Architecture

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration

A 65 nm CMOS Continuous-Time Pipeline ADC achieving 70 dB SNDR in 100 MHz Bandwidth

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration

A High Linearity T&H circuit for 1GHz Pipeline ADC in 65nm CMOS

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier

pipeline adc
Recently Published Documents