Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture

Instruction Format Design for Low Power Embedded Systems

Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

Peer instruction enhanced student performance on qualitative problem-solving questions

We tested the hypothesis that peer instruction enhances student performance on qualitative problem-solving questions. To test this hypothesis, qualitative problems were included in a peer instruction format during our Physiology course. Each class of 90 min was divided into four to six short segments of 15 to 20 min each. Each short segment was followed by a qualitative problem-solving scenario that could be answered with a multiple-choice quiz. All students were allowed 1 min to think and to record their answers. Subsequently, students were allowed 1 min to discuss their answers with classmates. Students were then allowed to change their first answer if desired, and both answers were recorded. Finally, the instructor and students discussed the answer. Peer instruction significantly improved student performance on qualitative problem-solving questions (59.3 ± 0.5% vs. 80.3 ± 0.4%). Furthermore, after peer instruction, only 6.5% of the students changed their correct response to an incorrect response; however, 56.8% of students changed their incorrect response to a correct response. Therefore, students with incorrect responses changed their answers more often than students with correct responses. In conclusion, pausing four to six times during a 90-min class to allow peer instruction enhanced student performance on qualitative problem-solving questions.

The Impact of Cognitive Organizers and Technology-Based Practices on Student Success in Secondary Social Studies Classrooms

This study investigated the impact of cognitive organizers, with the integration of technology, Inspiration 6 software, compared to a traditional textbook instruction format on content-area learning in high school inclusive social studies classes. Twenty-nine tenth-grade students in general education and 20 students with mild disabilities were randomly assigned to receive instruction using a cognitive organizer or traditional textbook instruction format. A pretest/posttest treatment control group design was used to examine the effectiveness of cognitive organizers. Dependent measures included a 35-item open-ended production pre/posttest of declarative social studies knowledge to assess the effectiveness of the intervention. Students in the cognitive organizer condition significantly outperformed students in the traditional textbook instruction condition. Limitations of the study, implications for practice for both general and special education teachers, and future research are discussed.