analog voltage
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Author(s):  
Anup Kumar Biswas

By manipulating an electron that tunnels the tunnel junction of a single electron transistor, one will be able to reach a standard output logic “1” or logic “0”. The operation of the Single Electron Transistor (SET) is depending upon the bias voltage as well as the input signal(s). By varying the input voltage levels of a SET, the output voltage levels can significantly be changed on the basis of tunneling of an electron whether tunneling happened or not. As our concentration is the measuring of an unknown voltage, we are to implement a voltmeter system to provide a digital output of 3 bits whenever an unknown input voltage is kept in touching in the input terminal. A reference/standard voltage (say 8mV) will be connected in series with eight resistances ( 8 Rs) for the purpose of making a seven threshold voltages, for 7 comparators, in an ascending order of values from ground to reference voltage for seven comparators which are used in this present work. The voltmeter implemented consists of (i) a voltage divider, (ii) a set of seven comparators, (iii) seven Exclusive-OR gates and (iv) three 4-input OR gates. The concepts of implementing “Parallel Comparator based voltmeter” is discussed in two ways (i) by classical block diagram and (ii) using Single electron transistor based circuit. The measuring of an input analog voltage will not be the same as the digital output value. A 3-bit output indicates that the input analog voltage must lie on within a particular small range of voltage. The encoder circuit which is connected to the outputs of the comparators is hard to construct whenever the three terminals output are expressed with the output variables (Wi) of the comparators. For simple and user-friendly circuit, the outputs (Wi) of the comparators are modified to Di variables so as to get the same 3-bit encoder/voltmeter output. For this purpose, 7 extra component called 2-input XORs based on SET are used. Seven such XORs are set, and the output of them are passed to three 4-input OR gates according to the required logic expressions. It is found that all the output data of the voltmeter are coherently matched with the theoretical aspects. Processing delays are found out for all circuits. Power consumptions of all of them are shown in tabular and graphical forms. All the circuit we are intending to make are provided in due places with their logic circuit or simulation set and the simulation results are provided as well. Different truth tables are given for keeping track of whether input-output relationships matches with the theoretical results. We have thought of whether the present work circuits are faster or slower than the circuits of CMOS based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 1×10^(-18) Joules to 22×10^(-18)Joules which is very small amount. All the combinational circuits presented in this work are of SET-based.


2021 ◽  
Author(s):  
Junyuan Shen ◽  
Huan Ding ◽  
Xiguo Ren ◽  
Shumin Ge ◽  
Yimin Wang ◽  
...  
Keyword(s):  

Author(s):  
Ashima Gupta ◽  
Anil Singh ◽  
Alpana Agarwal

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yasmin Halawani ◽  
Dima Kilani ◽  
Eman Hassan ◽  
Huruy Tesfai ◽  
Hani Saleh ◽  
...  

AbstractContent addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.


Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 922
Author(s):  
Seunghoon Ko

This paper presents a mutual capacitance touch readout IC architecture for 120 Hz high-refresh-rate AMOLED displays. In high-refresh-rate AMOLED panels, whole pixels in a horizontal line should be updated without any time-sharing with each other, leading to an amplified display noise on touch screen panel (TSP) electrodes. The proposed system architecture mitigates severe display noise by synchronizing the driving for the TSP and AMOLED pixel circuits. The proposed differential sensing technique, which is based on noise suppression in reference to mutual capacitance channels, minimizes common-mode display noise. In the front-end circuit, intrinsic circuit offset is cancelled by a chopping scheme, which correlates to the phase of the driving signals in the TSP driver and operating clocks of the front-end. Operating at a 120 Hz scan-rate, it reduces display noise by more than 11.6 dB when compared with the conventional single-ended TSP sensing method. With a built-in 130-nm CMOS, a prototype IC occupies an area of 8.02 mm2 while consuming 6.4-mW power from a 3.3 V analog voltage supply.


Sensors ◽  
2021 ◽  
Vol 21 (15) ◽  
pp. 5110
Author(s):  
Pisana Placidi ◽  
Renato Morbidelli ◽  
Diego Fortunati ◽  
Nicola Papini ◽  
Francesco Gobbi ◽  
...  

A low power wireless sensor network based on LoRaWAN protocol was designed with a focus on the IoT low-cost Precision Agriculture applications, such as greenhouse sensing and actuation. All subsystems used in this research are designed by using commercial components and free or open-source software libraries. The whole system was implemented to demonstrate the feasibility of a modular system built with cheap off-the-shelf components, including sensors. The experimental outputs were collected and stored in a database managed by a virtual machine running in a cloud service. The collected data can be visualized in real time by the user with a graphical interface. The reliability of the whole system was proven during a continued experiment with two natural soils, Loamy Sand and Silty Loam. Regarding soil parameters, the system performance has been compared with that of a reference sensor from Sentek. Measurements highlighted a good agreement for the temperature within the supposed accuracy of the adopted sensors and a non-constant sensitivity for the low-cost volumetric water contents (VWC) sensor. Finally, for the low-cost VWC sensor we implemented a novel procedure to optimize the parameters of the non-linear fitting equation correlating its analog voltage output with the reference VWC.


2021 ◽  
Author(s):  
Yasmin Halawani ◽  
Dima Kilani ◽  
Eman Hassan ◽  
Huruy Tesfai ◽  
Hani Saleh ◽  
...  

Abstract Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.


Author(s):  
Zhenrong Li ◽  
Jia Qiao ◽  
Yuxin Wang ◽  
Zeyuan Wang ◽  
Liyan Yu ◽  
...  
Keyword(s):  

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1141
Author(s):  
Mehdi Azadmehr ◽  
Luca Marchetti ◽  
Yngvar Berg

This paper presents a voltage similarity circuit (bump circuit) based on a novel voltage correlator. The proposed circuit is characterized by a power consumption which depends on the similarity between the two inputs. The sensitivity of the bump circuit and the power consumption are at the highest values when the inputs are equal. As the similarity between the input voltages decreases, the total current consumption decreases with a bell-shaped behavior. The proposed bump circuit is very simple in design, made of a new voltage correlator circuit in combination with a differential pair and mimics the behavior of the classical bump circuit. The voltage correlator was implemented using AMS−350nm CMOS technology. Simulation and measurement results suggests that a low power consumption may be achieved if the circuit is used in applications where the input signals have large dissimilarity for most of the circuit operation.


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