scholarly journals SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing

2022 ◽  
Vol 19 (1) ◽  
pp. 1-21
Author(s):  
Daeyeal Lee ◽  
Bill Lin ◽  
Chung-Kuan Cheng
Keyword(s):  
System Performance ◽  
Search Space ◽  
Satisfiability Modulo Theories ◽  
Low Latency ◽  
Task Mapping ◽  
Single Cycle ◽  
Space Reduction ◽  
Reduction Techniques ◽  
2D And 3D ◽  
Mixed Dimension

SMART NoCs achieve ultra-low latency by enabling single-cycle multiple-hop transmission via bypass channels. However, contention along bypass channels can seriously degrade the performance of SMART NoCs by breaking the bypass paths. Therefore, contention-free task mapping and scheduling are essential for optimal system performance. In this article, we propose an SMT (Satisfiability Modulo Theories)-based framework to find optimal contention-free task mappings with minimum application schedule lengths on 2D/3D SMART NoCs with mixed dimension-order routing. On top of SMT’s fast reasoning capability for conditional constraints, we develop efficient search-space reduction techniques to achieve practical scalability. Experiments demonstrate that our SMT framework achieves 10× higher scalability than ILP (Integer Linear Programming) with 931.1× (ranges from 2.2× to 1532.1×) and 1237.1× (ranges from 4× to 4373.8×) faster average runtimes for finding optimum solutions on 2D and 3D SMART NoCs and our 2D and 3D extensions of the SMT framework with mixed dimension-order routing also maintain the improved scalability with the extended and diversified routing paths, resulting in reduced application schedule lengths throughout various application benchmarks.

Search Space Reduction in Biometric Databases

2017 ◽  
pp. 236-262 ◽  
Author(s):  
Ilaiah Kavati ◽  
Munaga V. N. K. Prasad ◽  
Chakravarthy Bhagvati
Keyword(s):  
Response Time ◽  
Large Scale ◽  
Search Space ◽  
Comprehensive Review ◽  
Space Reduction ◽  
Reduction Techniques ◽  
Search Space Reduction ◽  
Search Speed ◽  
Personal Recognition ◽  
Real Time Applications

Deployment of biometrics for personal recognition in various real time applications lead to large scale databases. Identification of an individual on such large biometric databases using a one-one matching (i.e., exhaustive search) increases the response time of the system. Reducing the search space during identification increases the search speed and reduces the response time of the system. This chapter presents a comprehensive review of the current developments of the search space reduction techniques in biometric databases. Search space reduction techniques for the fingerprint databases are categorized into classification and indexing approaches. For the palmprint, the current search space reduction techniques are classified as hierarchical matching, classification and indexing approaches. Likewise, the iris indexing approaches are classified as texture based and color based techniques.

Search Space Reduction in Biometric Databases

2018 ◽  
pp. 1600-1626 ◽  
Author(s):  
Ilaiah Kavati ◽  
Munaga V. N. K. Prasad ◽  
Chakravarthy Bhagvati
Keyword(s):  
Response Time ◽  
Large Scale ◽  
Search Space ◽  
Comprehensive Review ◽  
Space Reduction ◽  
Reduction Techniques ◽  
Search Space Reduction ◽  
Search Speed ◽  
Personal Recognition ◽  
Real Time Applications

Deployment of biometrics for personal recognition in various real time applications lead to large scale databases. Identification of an individual on such large biometric databases using a one-one matching (i.e., exhaustive search) increases the response time of the system. Reducing the search space during identification increases the search speed and reduces the response time of the system. This chapter presents a comprehensive review of the current developments of the search space reduction techniques in biometric databases. Search space reduction techniques for the fingerprint databases are categorized into classification and indexing approaches. For the palmprint, the current search space reduction techniques are classified as hierarchical matching, classification and indexing approaches. Likewise, the iris indexing approaches are classified as texture based and color based techniques.

scholarly journals Faster sequence alignment through GPU-accelerated restriction of the seed-and-extend search space

2014 ◽  
Author(s):  
Richard Wilton ◽  
Tamas Budavari ◽  
Ben Langmead ◽  
Sarah J Wheelan ◽  
Steven Salzberg ◽  
...  
Keyword(s):  
Sequence Alignment ◽  
High Throughput ◽  
Search Space ◽  
Computational Effort ◽  
Biological Sequences ◽  
Reduction Techniques ◽  
Software Implementations ◽  
List Processing ◽  
High Processing

Motivation: In computing pairwise alignments of biological sequences, software implementations employ a variety of heuristics that decrease the computational effort involved in computing potential alignments. A key element in achieving high processing throughput is to identify and prioritize potential alignments where high-scoring mappings can be expected. These tasks involve list-processing operations that can be efficiently performed on GPU hardware. Results: We implemented a read aligner called A21 that exploits GPU-based parallel sort and reduction techniques to restrict the number of locations where potential alignments may be found. When compared with other high-throughput aligners, this approach finds more high-scoring mappings without sacrificing speed or accuracy. A21 running on a single GPU is about 10 times faster than comparable CPU-based tools; it is also faster and more sensitive in comparison with other recent GPU-based aligners.

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

2014 ◽  
pp. 368-398
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Task Mapping ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
Management Measures ◽  
Mapping Process ◽  
On Chip ◽  
And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

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