scholarly journals Twofold Addressing of Microinstructions in CMCU with Common Memory

2021 ◽  
pp. 86-98
Author(s):  
A. Barkalov ◽  
L. Titarenko ◽  
O. Golovin ◽  
A. Matvienko
Keyword(s):  
Power Consumption ◽  
Control Algorithm ◽  
Design Method ◽  
Optimal Solution ◽  
Control Unit ◽  
Digital Systems ◽  
Level Control ◽  
Chip Area ◽  
Control Circuits ◽  
Common Memory

Introduction. Control unit (CU) is one of the most important blocks of practically any digital system. Its characteristics largely determine the characteristics of a system as a whole. As a rule, to synthesize CUs, the models of Mealy and Moore finite state machines (FSMs) are used. The article is devoted to compositional microprogram control units (CMCUs). A CMCU is a Moore FSM in which a state register is replaced by a microinstruction address counter. The choice of CMCU is an optimal solution for implementing linear control algorithms. When developing FSM circuits, it is necessary to optimize such characteristics as the performance and hardware amount. The methods of optimization depend strongly on logic elements used. Nowadays, FPGA chips are one of the most common logic elements for implementing digital systems. To implement the CMCU circuit, it is enough to use look-up table (LUT) elements, programmable flip-flops, embedded memory blocks, and programmable interconnections. The purpose of the article. In the article, there is proposed a CMCU design method improving such characteristics of CU as the number of logic levels and regularity of programmable interconnections. The main drawback of LUT is a small number of inputs. Modern digital systems can generate signals of logical conditions entering the control unit, the number of which is tens of times greater than the number of LUT inputs. Such a discrepancy between the characteristics of the control algorithm and the number of inputs of the LUT elements leads to multi-level control circuits with an irregular structure of programmable interconnections, and is the reason for a decrease in performance and an increase in chip area and power consumption. Results. A method for double addressing of microinstructions in CMCU with shared memory is proposed. The method is an adaptation of the two-fold state assignment of Mealy FSMs, the circuits of which are implemented with FPGAs. The proposed method makes it possible to obtain a microinstruction addressing circuit with two logic levels and a regular interconnection system. The paper considers an example of the synthesis of the CMCU circuit and analyzes the proposed method. Conclusions. The proposed method allows reducing hardware amount (the number of LUTs and their interconnections), time of delay and power consumption. Moreover, the more complex the control algorithm, the greater the benefit the proposed method gives. Keywords: compositional microprogram control unit, microinstruction, LUT, EMB, synthesis.

The velocity regulation of power consumption with traffic lights for electric vehicles

2019 ◽  
Vol 233 (9) ◽  
pp. 2312-2322
Author(s):  
Qingwu Liu ◽  
Hongwen He
Keyword(s):  
Power Consumption ◽  
Travel Time ◽  
Electricity Consumption ◽  
Control Unit ◽  
Simulation Software ◽  
Traffic Information ◽  
Level Control ◽  
Long Distance ◽  
Traffic Lights ◽  
Traffic Conditions

Traffic conditions, especially at traffic crossings, have a great impact on the power consumption of vehicles. Regulating velocity using the information between vehicles and traffic systems can decrease the power consumption. This article mainly focuses on an electric vehicle equipped with radar sensors, which can get the traffic information from upto a 100-m-long distance between the controlled vehicle and the traffic lights. Using the information gathered from sensors, the top-level control unit regulates the velocity aiming at lower power consumption. When traveling through crossings, two different traffic conditions are discussed. For the first condition, no other vehicles run between the controlled vehicle and the traffic lights. Only the traffic lights information is considered. For the second condition, the controlled vehicle follows other vehicles to go through the crossing. The information of the nearest front vehicle and traffic lights is taken into consideration. In summary, the traffic lights information, including the controlled vehicle current state, the traffic lights remaining time, and the velocity and distance of the nearest former vehicle (for the second condition) are sent to the top-level control unit. Then, the control unit calculates a velocity list, which will be sent to the vehicle control unit. A simulation is conducted using a traffic simulation software named “Simulation of Urban Mobility” to verify the algorithm. The simulation results indicate that the energy efficiency is improved. For the first condition, the travel time is reduced by 8.27%, and the power consumption is reduced by 18.7%. For the second condition, the power consumption is reduced by 2.96%. Finally, for a 5.8-km driving cycle containing both conditions, the travel time is reduced by 6.9% and electricity consumption is reduced by 9.51%.

A Model of Caterpillar Locomotion Based on Assur Tensegrity Structures

2011 ◽  
Author(s):  
Omer Orki ◽  
Offer Shai ◽  
Amir Ayali ◽  
Uri Ben-Hanan
Keyword(s):  
Hydrostatic Pressure ◽  
Control Algorithm ◽  
Control Unit ◽  
Engineering Properties ◽  
Level Control ◽  
Tensegrity Structures ◽  
Control Scheme ◽  
High Level ◽  
Longitudinal Muscles ◽  
Ongoing Project

This paper presents an ongoing project aiming at building a robot composed of Assur tensegrity structures, which mimics caterpillar locomotion. Caterpillars are soft-bodied animals capable of making complex movements with astonishing fault-tolerance. In our model, each caterpillar segment is represented by a 2D tensegrity triad consisting of two bars connected by two cables and a strut. The cables represent the major longitudinal muscles of the caterpillar, while the strut represents hydrostatic pressure. The control scheme in this model is divided into localized low-level controllers and a high-level control unit. The unique engineering properties of Assur tensegrity structures, which were mathematically proved last year, together with the suggested control algorithm provide the model with robotic softness. Moreover, the degree of softness can be continuously changed during simulation, making this model suitable for simulation of soft-bodied caterpillars as well as other types of soft animals.

scholarly journals Reducing LUT Count for FPGA-Based Mealy FSMs

2020 ◽  
Vol 10 (15) ◽  
pp. 5115 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Kazimierz Krzywicki
Keyword(s):  
Power Consumption ◽  
Finite State Machine ◽  
Design Method ◽  
Logic Circuits ◽  
Digital Systems ◽  
Single Level ◽  
Small Loss ◽  
Finite State ◽  
Methods Of Synthesis ◽  
Novel Design

Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

scholarly journals Optimization of a Composition Microprogram Control Unit with Elementary Circuits

2021 ◽  
pp. 40-51
Author(s):  
Oleksandr O. Barkalov ◽  
◽  
Larisa O. Titarenko ◽  
Oleksandr M. Golovin ◽  
Oleksandr V. Matvienko ◽  
...  
Keyword(s):  
Power Consumption ◽  
Control Unit ◽  
Digital Systems ◽  
Software Modeling ◽  
Control Units ◽  
Field Programmable ◽  
Equivalent Control ◽  
Rational Organization ◽  
Hardware Costs ◽  
Elementary Basis

Introduction. The control unit coordinating interaction of all other blocks of a digital system is one of the central blocks and is a sequential circuit. As a rule, when synthesizing control unit circuits, the problem arises of reducing hardware costs. Methods for solving this problem depend on features of both the architecture of the control unit and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control units of digital systems by taking into account features of the element base of the control unit and rational organization of addressing microinstructions. FPGA (field-programmable logic array) microcircuits, widely used for the implementation of modern digital systems, were chosen as an elementary basis. Methods. Methods of set theory, synthesis of automata, and software modeling as well as the library of standard automata and FPGA Virtex-7 from Xilinx were used for assessment the effectiveness of solving the problem. Results. The paper proposes a method for optimizing the circuit of the microinstruction addressing unit based on splitting the set of outputs of elementary linear operator circuits, which is based on the idea of double coding of states. The proposed method, under certain conditions, makes it possible to reduce the number of levels in the microinstruction addressing circuit to two. Conclusion. Studies have shown that double coding of states can increase performance, reduce hardware costs (the number of LUTs and their interconnections) and power consumption in Mealy’s circuitry. Based on these results, it can be expected that, with the number of conditions exceeding the number of LUT inputs, the proposed approach will improve the characteristics of the composition microprogram control unit in comparison with the equivalent control unit U1.

scholarly journals A Metaheuristic Algorithm for VLSI Floorplanning Problem

2019 ◽  
Vol 8 (2S5) ◽  
pp. 249-254
Keyword(s):  
Genetic Algorithm ◽  
Large Scale ◽  
Search Algorithm ◽  
Design Method ◽  
Harmony Search ◽  
Optimal Solution ◽  
Harmony Search Algorithm ◽  
Chip Area ◽  
Optimum Solution ◽  
Vlsi Floorplanning

Floorplanning plays an important role within the physical design method of very large Scale Integrated (VLSI) chips. It’s a necessary design step to estimate the chip area before the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, several improvement techniques were adopted to find optimal solution. In this paper, a hybrid algorithm which is genetic algorithm combined with music-inspired Harmony Search (HS) algorithm is employed for the fixed die outline constrained floorplanning, with the ultimate aim of reducing the full chip area. Initially, B*-tree is employed to come up with the first floorplan for the given rectangular hard modules and so Harmony Search algorithm is applied in any stages in genetic algorithm to get an optimum solution for the economical floorplan. The experimental results of the HGA algorithm are obtained for the MCNC benchmark circuits

scholarly journals Power optimization of digital baseband WCDMA receiver components on algorithmic and architectural level

2008 ◽  
Vol 6 ◽  
pp. 325-330 ◽  
Author(s):  
M. Schämann ◽  
M. Bücker ◽  
S. Hessel ◽  
U. Langmann
Keyword(s):  
Power Consumption ◽  
Control Unit ◽  
Design Flow ◽  
Peak Performance ◽  
Chip Area ◽  
High Data ◽  
Operating Modes ◽  
Data Rates ◽  
High Data Rates ◽  
Ber Performance

Abstract. High data rates combined with high mobility represent a challenge for the design of cellular devices. Advanced algorithms are required which result in higher complexity, more chip area and increased power consumption. However, this contrasts to the limited power supply of mobile devices. This presentation discusses the application of an HSDPA receiver which has been optimized regarding power consumption with the focus on the algorithmic and architectural level. On algorithmic level the Rake combiner, Prefilter-Rake equalizer and MMSE equalizer are compared regarding their BER performance. Both equalizer approaches provide a significant increase of performance for high data rates compared to the Rake combiner which is commonly used for lower data rates. For both equalizer approaches several adaptive algorithms are available which differ in complexity and convergence properties. To identify the algorithm which achieves the required performance with the lowest power consumption the algorithms have been investigated using SystemC models regarding their performance and arithmetic complexity. Additionally, for the Prefilter Rake equalizer the power estimations of a modified Griffith (LMS) and a Levinson (RLS) algorithm have been compared with the tool ORINOCO supplied by ChipVision. The accuracy of this tool has been verified with a scalable architecture of the UMTS channel estimation described both in SystemC and VHDL targeting a 130 nm CMOS standard cell library. An architecture combining all three approaches combined with an adaptive control unit is presented. The control unit monitors the current condition of the propagation channel and adjusts parameters for the receiver like filter size and oversampling ratio to minimize the power consumption while maintaining the required performance. The optimization strategies result in a reduction of the number of arithmetic operations up to 70% for single components which leads to an estimated power reduction of up to 40% while the BER performance is not affected. This work utilizes SystemC and ORINOCO for the first estimation of power consumption in an early step of the design flow. Thereby algorithms can be compared in different operating modes including the effects of control units. Here an algorithm having higher peak complexity and power consumption but providing more flexibility showed less consumption for normal operating modes compared to the algorithm which is optimized for peak performance.

The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

2009 ◽  
Vol E92-C (3) ◽  
pp. 352-355
Author(s):  
Ki-Sang JUNG ◽  
Kang-Jik KIM ◽  
Young-Eun KIM ◽  
Jin-Gyun CHUNG ◽  
Ki-Hyun PYUN ◽  
...  
Keyword(s):  
Power Consumption ◽  
Compression Method ◽  
Chip Area ◽  
Consumption Reduction

Research on Fuzzy Control of Mine Ventilation Based on Embedded Systems

2014 ◽  
Vol 686 ◽  
pp. 126-131
Author(s):  
Xiao Yan Sha
Keyword(s):  
Fuzzy Control ◽  
Control Algorithm ◽  
Fuzzy Controller ◽  
Simulation Analysis ◽  
Control Unit ◽  
Real Time Control ◽  
Embedded Processor ◽  
Feed Forward ◽  
Time Control ◽  
Software And Hardware

Taking embedded processor as the core control unit, the paper designs the fan monitoring system software and hardware to achieve the fan working condition detection and real-time control. For the control algorithm, the paper analyzes the fuzzy control system theory and composition, and then combined with tunnel ventilation particularity, introduce feed-forward model to predict the incremental acquisition of pollutants to reduce lag, combined with the system feedback value and the set value, by calculate of two independent computing fuzzy controller, and ultimately determine the number of units increase or decrease in the tunnel jet fans start and stop. Through simulation analysis, the introduction of a feed-forward signal, it can more effectively improve the capability of the system impact of interference.

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