scholarly journals Optimization of a Composition Microprogram Control Unit with Elementary Circuits

2021 ◽  
pp. 40-51
Author(s):  
Oleksandr O. Barkalov ◽  
◽  
Larisa O. Titarenko ◽  
Oleksandr M. Golovin ◽  
Oleksandr V. Matvienko ◽  
...  
Keyword(s):  
Power Consumption ◽  
Control Unit ◽  
Digital Systems ◽  
Software Modeling ◽  
Control Units ◽  
Field Programmable ◽  
Equivalent Control ◽  
Rational Organization ◽  
Hardware Costs ◽  
Elementary Basis

Introduction. The control unit coordinating interaction of all other blocks of a digital system is one of the central blocks and is a sequential circuit. As a rule, when synthesizing control unit circuits, the problem arises of reducing hardware costs. Methods for solving this problem depend on features of both the architecture of the control unit and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control units of digital systems by taking into account features of the element base of the control unit and rational organization of addressing microinstructions. FPGA (field-programmable logic array) microcircuits, widely used for the implementation of modern digital systems, were chosen as an elementary basis. Methods. Methods of set theory, synthesis of automata, and software modeling as well as the library of standard automata and FPGA Virtex-7 from Xilinx were used for assessment the effectiveness of solving the problem. Results. The paper proposes a method for optimizing the circuit of the microinstruction addressing unit based on splitting the set of outputs of elementary linear operator circuits, which is based on the idea of double coding of states. The proposed method, under certain conditions, makes it possible to reduce the number of levels in the microinstruction addressing circuit to two. Conclusion. Studies have shown that double coding of states can increase performance, reduce hardware costs (the number of LUTs and their interconnections) and power consumption in Mealy’s circuitry. Based on these results, it can be expected that, with the number of conditions exceeding the number of LUT inputs, the proposed approach will improve the characteristics of the composition microprogram control unit in comparison with the equivalent control unit U1.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

scholarly journals Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

2019 ◽  
Vol 8 (9S2) ◽  
pp. 530-533
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
Control Unit ◽  
Processing Unit ◽  
Power Efficient ◽  
Central Processing ◽  
Unit Design ◽  
Efficient Control ◽  
Field Programmable

These works describe the implementation of a control unit which is an important part of Central Processing Unit (CPU) with the Field Programmable Gate Array (FPGA). In this work a frequency scaled and thermal aware energy-efficient control unit is designed with the help of 28 nanometer (nm) technology based FPGA. Frequency varies from 100MHz to 5GHz and the rise in frequency also gives rise in power consumption of control unit with FPGA. The thermal properties of FPGA also increase with increment in frequency. This whole experiment is done on Xilinx 14.1 ISE Design Suit and it is observed that lower the frequency, lower will be the power consumption of FPGA.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA.

scholarly journals Twofold Addressing of Microinstructions in CMCU with Common Memory

2021 ◽  
pp. 86-98
Author(s):  
A. Barkalov ◽  
L. Titarenko ◽  
O. Golovin ◽  
A. Matvienko
Keyword(s):  
Power Consumption ◽  
Control Algorithm ◽  
Design Method ◽  
Optimal Solution ◽  
Control Unit ◽  
Digital Systems ◽  
Level Control ◽  
Chip Area ◽  
Control Circuits ◽  
Common Memory

Introduction. Control unit (CU) is one of the most important blocks of practically any digital system. Its characteristics largely determine the characteristics of a system as a whole. As a rule, to synthesize CUs, the models of Mealy and Moore finite state machines (FSMs) are used. The article is devoted to compositional microprogram control units (CMCUs). A CMCU is a Moore FSM in which a state register is replaced by a microinstruction address counter. The choice of CMCU is an optimal solution for implementing linear control algorithms. When developing FSM circuits, it is necessary to optimize such characteristics as the performance and hardware amount. The methods of optimization depend strongly on logic elements used. Nowadays, FPGA chips are one of the most common logic elements for implementing digital systems. To implement the CMCU circuit, it is enough to use look-up table (LUT) elements, programmable flip-flops, embedded memory blocks, and programmable interconnections. The purpose of the article. In the article, there is proposed a CMCU design method improving such characteristics of CU as the number of logic levels and regularity of programmable interconnections. The main drawback of LUT is a small number of inputs. Modern digital systems can generate signals of logical conditions entering the control unit, the number of which is tens of times greater than the number of LUT inputs. Such a discrepancy between the characteristics of the control algorithm and the number of inputs of the LUT elements leads to multi-level control circuits with an irregular structure of programmable interconnections, and is the reason for a decrease in performance and an increase in chip area and power consumption. Results. A method for double addressing of microinstructions in CMCU with shared memory is proposed. The method is an adaptation of the two-fold state assignment of Mealy FSMs, the circuits of which are implemented with FPGAs. The proposed method makes it possible to obtain a microinstruction addressing circuit with two logic levels and a regular interconnection system. The paper considers an example of the synthesis of the CMCU circuit and analyzes the proposed method. Conclusions. The proposed method allows reducing hardware amount (the number of LUTs and their interconnections), time of delay and power consumption. Moreover, the more complex the control algorithm, the greater the benefit the proposed method gives. Keywords: compositional microprogram control unit, microinstruction, LUT, EMB, synthesis.

scholarly journals D-PMU and 5G-Network-Based Coordination Control Method for Three-Phase Imbalance Mitigation Units in the LVDN

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2754
Author(s):  
Mengmeng Xiao ◽  
Shaorong Wang ◽  
Zia Ullah
Keyword(s):  
Mobile Networks ◽  
Control Method ◽  
Low Voltage ◽  
Control Unit ◽  
Distribution Networks ◽  
Optimal Operation ◽  
Positive Sequence ◽  
Measurement Unit ◽  
Control Units ◽  
Three Phase

Three-phase imbalance is a long-term issue existing in low-voltage distribution networks (LVDNs), which consequently has an inverse impact on the safe and optimal operation of LVDNs. Recently, the increasing integration of single-phase distributed generations (DGs) and flexible loads has increased the probability of imbalance occurrence in LVDNs. To overcome the above challenges, this paper proposes a novel methodology based on the concept of "Active Asymmetry Energy-Absorbing (AAEA)" utilizing loads with a back-to-back converter, denoted as “AAEA Unit” in this paper. AAEA Units are deployed and coordinated to actively absorb asymmetry power among three phases for imbalance mitigation in LVDNs based on the high-precision, high-accuracy, and real-time distribution-level phasor measurement unit (D-PMU) data acquisition system and the 5th generation mobile networks (5G) communication channels. Furthermore, the control scheme of the proposed method includes three control units. Specifically, the positive-sequence control unit is designed to maintain the voltage of the DC-capacitor of the back-to-back converter. Likewise, the negative-sequence and zero-sequence control units are expected to mitigate the imbalanced current components. A simple imbalanced LVDN is modeled and tested in Simulink/Matlab (MathWorks, US). The obtained results demonstrate the effectiveness of the proposed methodology.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

Optimisation of a Polarisation Nephelometer

2021 ◽  
pp. 87-95
Author(s):  
Victor G. Oshlakov ◽  
Anatoly P. Shcherbakov
Keyword(s):  
Personal Computer ◽  
Position Control ◽  
Control Unit ◽  
Numerical Control ◽  
Radiation Beam ◽  
Drive Control ◽  
Control Units ◽  
Smooth Motion ◽  
Approximation Errors ◽  
Scattering Volume

An analysis of the influence caused by polarization nephelometer parameters on the scattering matrix measurement accuracy in a non-isotropic medium is presented. The approximation errors in the actual scattering volume and radiation beam by an elementary scattering volume and an elementary radiation beam are considered. A formula for calculating the nephelometer base is proposed. It is shown that requirements to an irradiation source of a polarizing nephelometer, i.e. mono-chromaticity and high radiation intensity and directivity in a wide spectral range can be satisfied by a set of high brightness LEDs with a radiating (self-luminous) small size body. A 5-wavelength monochromatic irradiation source, with an emission flux of (0.15–0.6) W required for a polarization nephelometer, is described. The design of small-sized polarizing phase control units is shown. An electronic circuit of a radiator control unit based on an AVR-Atmega 8-bit microcontroller with feedback and drive control realized by means of an incremental angular motion sensor and a software PID controller is presented. Precise and smooth motion of the radiator is ensured by standard servo-driven numerical control mathematics and the use of precision gears. The system allows both autonomous adjustment of the radiator’s reference positions and adjustment by means of commands from a personal computer. Both the computer and microcontroller programs were developed with the use of free software, making it possible to transfer the programs to Windows‑7(10), Linux and embedded Linux operating systems. Communication between the radiator’s position control system and the personal computer is realised by means of a standard noise immune USB-RS485 interface.

Sign in / Sign up

Export Citation Format

Share Document