Design of Hybrid Schottky-Ohmic Gate in Normally-Off p-GaN Gate AlGaN/GaN HEMTs

This study proposes three hybrid Schottky-ohmic gate structures for normally-off p-GaN gate AlGaN/GaN HEMTs. One has a Schottky-gate cover on the ohmic-gate and has part of the area contact to the p-GaN surface at the left and right sides of ohmic-gate (Structure A). The two others only have the Schottky-gate contact to the p-GaN surface at the left side (Structure B) or right side (Structure C) of the ohmic-gate. Different gate metal designs change the hole injection from p-GaN to GaN channel and show various gate leakages. The optimized contact length of Schottky-gate can suppress on-state gate leakage current over two orders of magnitude compared to conventional ohmic p-GaN gate HEMT. The improved on-state maximum drain current is over 60 mA/mm compared to Schottky p-GaN gate HEMT. Optimal performance in Structure B with Schottky-gate contact length ranges from 0.8 to 1.8 μm in a 2 μm gate geometry.

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-k/Metal-Gate Device

In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering

In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of −3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10−10 A/mm.