A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process

We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.

A novel optimization approach for partitioning-based place and route in 3D integrated circuits

The 3D integrated circuits are enlarging the technology with lots of potentials which establish vertical interconnection between different dies or layers. In 3D-integrated circuit fabrication, congestion, and wirelength minimization are challenging processes. To overcome these problems, we proposed a novel optimization approach for useful partitioning, placement, and routing. Our proposed work consists of four significant stages, including partitioning, placement, routing, and fault diagnosis in through silicon via and spare through silicon via allocation. Firstly, the QuadTree partitioning method executed by the partitioning process. QuadTree method partitions the layer into four subdivisions and remains until it finds no space for partitioning. AND logic is proposed to overcome the congestion problem during placement. In the second stage, the functioning of the hybrid particle swarm optimization and simulated annealing algorithm proposed by the placement process. Particle swarm optimization computes fitness function for six constraints, specifically wirelength, area, power, cross talk, temperature, and delay. The simulated annealing places circuits in the specified area with the computed fitness function. In every 45°, Kruskal’s based octi-linear Steiner tree algorithm that establishes routes performs the routing by the third stage. In the last stage, fault detection in through silicon via and spare through silicon via allocation processes are executed using the support vector machine algorithm and dedicated switch. Support vector machine classifies the TSV into two, which includes regular and redundant through silicon via. The spare through silicon via allocation performed by using a dedicated switch. Finally, the proposed work evaluated based on metrics such as wire length, area, temperature, delay, and run time.

Low Temperature Nickel Induced Crystallization of Amorphous Silicon Nanorods on Silicon and Glass Substrates

In this work, crystallization of amorphous silicon (a-Si) nanorods was done by metal induced crystallization (MIC) method at low temperature (500oC) suitable for circuit applications and low cost, disposable biosensors. The crystallization of a-Si nanorods was investigated by Raman and TEM methods. These data showed oriented crystallized Si nanorods have been obtained by metal induced crystallization (MIC) method on different substrates, which can be suitable for 3D integrated circuits, optical and electrochemical applications. This simple method can be used to produce silicon nanorod arrays with high quality suitable for nanoelectronic and optoelectronic applications.