Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip

For years, DSP has been the dominant tool in implementing gate switching for power inverter. It is a powerful and reliable technology in carrying out complex switching schemes. DSP is still expensive due to its intensive use of resource in chip fabrication. There is no flexibility in making change on hardware once a DSP chip is selected. It is also time consuming in a design development because the learning curve of the DSP is stiff. Recently, a new approach to the problem has emerged. It is called embedded system design. Basically, it is a FPGA system combined with a RISC type microprocessor. This is a robust combination that allows users to pick and choose any functional peripheral devices only as needed. Once the complete hardware platform is decided upon, the circuit is configured and down loaded to a chip. Software codes are then written to run the application. The hardware system is reconfigurable. Designers can always go back to change the hardware with ease in order to improve the performance and to meet the target cost. This is an attempt to utilize the embedded system design also called System on Programmable Chip (SOPC) to perform Space Vector Modulation (SVM) gate switching strategy. The Altera Nios II IDE tool is selected for this task.

Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip

For years, DSP has been the dominant tool in implementing gate switching for power inverter. It is a powerful and reliable technology in carrying out complex switching schemes. DSP is still expensive due to its intensive use of resource in chip fabrication. There is no flexibility in making change on hardware once a DSP chip is selected. It is also time consuming in a design development because the learning curve of the DSP is stiff. Recently, a new approach to the problem has emerged. It is called embedded system design. Basically, it is a FPGA system combined with a RISC type microprocessor. This is a robust combination that allows users to pick and choose any functional peripheral devices only as needed. Once the complete hardware platform is decided upon, the circuit is configured and down loaded to a chip. Software codes are then written to run the application. The hardware system is reconfigurable. Designers can always go back to change the hardware with ease in order to improve the performance and to meet the target cost. This is an attempt to utilize the embedded system design also called System on Programmable Chip (SOPC) to perform Space Vector Modulation (SVM) gate switching strategy. The Altera Nios II IDE tool is selected for this task.