Journal of Signal Processing Systems
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Published By Springer-Verlag

1939-8115, 1939-8018

Author(s):  
Omiya Hassan ◽  
Tanmoy Paul ◽  
Maruf Hossain Shuvo ◽  
Dilruba Parvin ◽  
Rushil Thakker ◽  
...  

Author(s):  
Simo Särkkä ◽  
Lassi Roininen ◽  
Manon Kok ◽  
Roland Hostettler ◽  
Andreas Hauptmann

Author(s):  
Christoph Spang ◽  
Yannick Lavan ◽  
Marco Hartmann ◽  
Florian Meisel ◽  
Andreas Koch

AbstractThe Dynamic Execution Integrity Engine (DExIE) is a lightweight hardware monitor that can be flexibly attached to many IoT-class processor pipelines. It is guaranteed to catch both inter- and intra-function illegal control flows in time to prevent any illegal instructions from touching memory. The performance impact of attaching DExIE to a core depends on the concrete pipeline structure. In some especially suitable cases, extending a processor with DExIE will have no performance penalty. DExIE is real-time capable, as it causes no or only up to 10.4 % additional and then predictable pipeline stalls. Depending on the monitored processor’s size and structure, DExIE is faster than software-based monitoring and often smaller than a separate guard processor. We present not just the hardware architecture, but also the automated programming flow, and discuss compact adaptable storage formats to hold fine-grained control flow information.


Author(s):  
Joanna Stanisz ◽  
Konrad Lis ◽  
Marek Gorgon

AbstractIn this paper, we present a hardware-software implementation of a deep neural network for object detection based on a point cloud obtained by a LiDAR sensor. The PointPillars network was used in the research, as it is a reasonable compromise between detection accuracy and calculation complexity. The Brevitas / PyTorch tools were used for network quantisation (described in our previous paper) and the FINN tool for hardware implementation in the reprogrammable Zynq UltraScale+ MPSoC device. The obtained results show that quite a significant computation precision limitation along with a few network architecture simplifications allows the solution to be implemented on a heterogeneous embedded platform with maximum 19% AP loss in 3D, maximum 8% AP loss in BEV and execution time 375ms (the FPGA part takes 262ms). We have also compared our solution in terms of inference speed with a Vitis AI implementation proposed by Xilinx (19 Hz frame rate). Especially, we have thoroughly investigated the fundamental causes of differences in the frame rate of both solutions. The code is available at https://github.com/vision-agh/pp-finn.


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