scholarly journals CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse

2007 ◽  
pp. 154-168
Author(s):  
Lilian Janin ◽  
Doug Edwards
Keyword(s):  
Transaction Level Modeling ◽  
Transaction Level ◽  
Ip Reuse

scholarly journals Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

2005 ◽  
Vol 10 (2-3) ◽  
pp. 105-125 ◽  
Author(s):  
Nagu Dhanwada ◽  
Reinaldo A. Bergamaschi ◽  
William W. Dungan ◽  
Indira Nair ◽  
Paul Gramann ◽  
...  
Keyword(s):  
Power Analysis ◽  
Transaction Level Modeling ◽  
Transaction Level

Transaction Level Modeling

2011 ◽  
pp. 25-36 ◽  
Author(s):  
Sandro Rigo ◽  
Bruno Albertini ◽  
Rodolfo Azevedo
Keyword(s):  
Transaction Level Modeling ◽  
Transaction Level

Application Specific Architecture Template Reuse for SoC Transaction Level Modeling

2012 ◽  
Vol 198-199 ◽  
pp. 911-916
Author(s):  
Da Wei Wang ◽  
Si Kun Li
Keyword(s):  
System Level ◽  
Transaction Level Modeling ◽  
System Level Modeling ◽  
Transaction Level ◽  
Application Specific

In the field of SoC hardware/software co-design, transaction level modeling is the bridge of SoC system level modeling and RTL level modeling. This paper considers a novel application specific template reuse approach for SoC transaction level modeling. Application specific architecture templates are built by integrating computation, communication and scheduling IP modules. These templates can support SoC modeling, mapping and simulation simultaneously. Experiments results from JPEG encoder applications in TL_Platform Creator show the approach can improve the quality and efficiency of SoC design greatly.

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