Translation Validation of Loop Optimizations and Software Pipelining in the TVOC Framework

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1145/500001.500052 ◽

2001 ◽

Cited By ~ 5

Author(s):

Noureddine Chabini ◽

Yvon Savaria

Keyword(s):

Software Pipelining ◽

Synchronous Circuits

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Validating More Loop Optimizations

Electronic Notes in Theoretical Computer Science ◽

10.1016/j.entcs.2005.02.044 ◽

2005 ◽

Vol 141 (2) ◽

pp. 69-84 ◽

Cited By ~ 2

Author(s):

Ying Hu ◽

Clark Barrett ◽

Benjamin Goldberg ◽

Amir Pnueli

Keyword(s):

Loop Optimizations

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Register-sensitive software pipelining

Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing ◽

10.1109/ipps.1998.669910 ◽

2002 ◽

Cited By ~ 13

Author(s):

A.K. Dani ◽

V. Janaki Ramanan ◽

R. Govindarajan

Keyword(s):

Software Pipelining

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Dataflow software pipelining: a case study

Ninth Annual International Phoenix Conference on Computers and Communications. 1990 Conference Proceedings ◽

10.1109/pccc.1990.101718 ◽

1990 ◽

Author(s):

G.R. Gao ◽

Z. Paraskevas

Keyword(s):

Software Pipelining

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Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set

10.1109/candarw53999.2021.00022 ◽

2021 ◽

Author(s):

Jixin Han ◽

Tomofumi Yuki ◽

Michelle Mills Strout ◽

Dan Umeda ◽

Hironori Kasahara ◽

...

Keyword(s):

Parallelizing Compiler ◽

Task Set ◽

Translation Validation ◽

And Task

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Material Translation: Validation and Visualization as Transdisciplinary Methods for Textile Design and Materials Science in the Circular Bioeconomy

Journal of Textile Design Research and Practice ◽

10.1080/20511787.2018.1467206 ◽

2018 ◽

Vol 6 (1) ◽

pp. 66-88

Author(s):

Miriam Ribul ◽

Hanna de la Motte

Keyword(s):

Materials Science ◽

Textile Design ◽

Translation Validation

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Loop Optimizations

Modern Compiler Implementation in C ◽

10.1017/cbo9781139174930.019 ◽

1997 ◽

pp. 410-432

Keyword(s):

Loop Optimizations

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Research of Register Pressure Aware Loop Unrolling Optimizations for Compiler

MATEC Web of Conferences ◽

10.1051/matecconf/201822803008 ◽

2018 ◽

Vol 228 ◽

pp. 03008

Author(s):

Xuehua Liu ◽

Liping Ding ◽

Yanfeng Li ◽

Guangxuan Chen ◽

Jin Du

Keyword(s):

Finite Number ◽

Infinite Number ◽

Performance Degradation ◽

Transformation Process ◽

Fine Grained ◽

Loop Unrolling ◽

Average Improvement ◽

Register Pressure ◽

Linpack Benchmark ◽

Loop Optimizations

Register pressure problem has been a known problem for compiler because of the mismatch between the infinite number of pseudo registers and the finite number of hard registers. Too heavy register pressure may results in register spilling and then leads to performance degradation. There are a lot of optimizations, especially loop optimizations suffer from register spilling in compiler. In order to fight register pressure and therefore improve the effectiveness of compiler, this research takes the register pressure into account to improve loop unrolling optimization during the transformation process. In addition, a register pressure aware transformation is able to reduce the performance overhead of some fine-grained randomization transformations which can be used to defend against ROP attacks. Experiments showed a peak improvement of about 3.6% and an average improvement of about 1% for SPEC CPU 2006 benchmarks and a peak improvement of about 3% and an average improvement of about 1% for the LINPACK benchmark.

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