Worst-Case Communication Delay Analysis for NoC-Based Many-Cores Using a Limited Migrative Model

Journal of Signal Processing Systems ◽

10.1007/s11265-015-0992-6 ◽

2015 ◽

Vol 84 (1) ◽

pp. 25-46 ◽

Author(s):

Borislav Nikolić ◽

Patrick Meumeu Yomsi ◽

Stefan M. Petters

Keyword(s):

Communication Delay ◽

Delay Analysis ◽

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Worst-case communication delay analysis for many-cores using a Limited Migrative Model

2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications ◽

10.1109/rtcsa.2014.6910498 ◽

2014 ◽

Author(s):

Borislav Nikolic ◽

Patrick Meumeu Yomsi ◽

Stefan M. Petters

Keyword(s):

Communication Delay ◽

Delay Analysis ◽

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Model for worst case delay analysis of an AFDX network using timed automata

2010 IEEE 15th Conference on Emerging Technologies & Factory Automation (ETFA 2010) ◽

10.1109/etfa.2010.5641124 ◽

2010 ◽

Author(s):

Muhammad Adnan ◽

Jean-Luc Scharbarg ◽

Jérôme Ermont ◽

Christian Fraboul

Keyword(s):

Timed Automata ◽

Delay Analysis ◽

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Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores

10th IEEE International Symposium on Industrial Embedded Systems (SIES) ◽

10.1109/sies.2015.7185041 ◽

2015 ◽

Author(s):

Laure Abdallah ◽

Mathieu Jan ◽

Jerome Ermont ◽

Christian Fraboul

Keyword(s):

Delay Analysis ◽

Wormhole Networks

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Communication delay analysis of fault-tolerant pipelined circuit switching in torus

Journal of Computer and System Sciences ◽

10.1016/j.jcss.2007.02.003 ◽

2007 ◽

Vol 73 (8) ◽

pp. 1131-1144 ◽

Author(s):

F. Safaei ◽

A. Khonsari ◽

M. Fathy ◽

M. Ould-Khaoua

Keyword(s):

Fault Tolerant ◽

Communication Delay ◽

Delay Analysis ◽

Circuit Switching ◽

Pipelined Circuit Switching

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Worst-Case End-to-End Delay Analysis for an AFDX Evolution Network

2020 IEEE 6th International Conference on Computer and Communications (ICCC) ◽

10.1109/iccc51575.2020.9344991 ◽

2020 ◽

Author(s):

Xueqian Tang ◽

Zexiong Luo ◽

Guoyuan Qu

Keyword(s):

Delay Analysis ◽

End To End Delay ◽

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Worst-case delay analysis of master-slave switched ethernet networks

Proceeings of the 2nd International Workshop on Worst-Case Traversal Time - WCTT '12 ◽

10.1145/2428592.2428595 ◽

2012 ◽

Author(s):

M. Ashjaei ◽

M. Liu ◽

M. Behnam ◽

A. Mifdaoui ◽

L. Almeida ◽

...

Keyword(s):

Delay Analysis ◽

Switched Ethernet ◽

Ethernet Networks

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Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling

2011 Design, Automation & Test in Europe ◽

10.1109/date.2012.6176457 ◽

2012 ◽

Author(s):

F. Jafari ◽

A. Jantsch ◽

Zhonghai Lu

Keyword(s):

Network On Chip ◽

Delay Analysis ◽

Variable Bit Rate ◽

Bit Rate ◽

Aggregate Scheduling ◽

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Worst case delay analysis of shared resource access in partitioned multi-core systems

Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia - ESTIMedia '17 ◽

10.1145/3139315.3139322 ◽

2017 ◽

Author(s):

Donghyun Kang ◽

Junchul Choi ◽

Soonhoi Ha

Keyword(s):

Delay Analysis ◽

Shared Resource ◽

Resource Access

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A Revised Trajectory Approach for the Worst-Case Delay Analysis of an AFDX Network

IEEE Access ◽

10.1109/access.2019.2943543 ◽

2019 ◽

Vol 7 ◽

pp. 142564-142573

Author(s):

Xueqian Tang ◽

Qiao Li ◽

Guangshan Lu ◽

Huagang Xiong

Keyword(s):

Delay Analysis ◽

Trajectory Approach

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Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise

2013 22nd Asian Test Symposium ◽

10.1109/ats.2013.17 ◽

2013 ◽

Author(s):

Fang Bao ◽

Mohammad Tehranippor ◽

Harry Chen

Keyword(s):

Power Supply ◽

Critical Path ◽

Delay Analysis ◽

Power Supply Noise ◽

Critical Path Delay ◽

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