Design and performance evaluation of Mesh-of-Tree-based hierarchical wireless network-on-chip for multicore systems

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2018.09.008 ◽

2019 ◽

Vol 123 ◽

pp. 100-117 ◽

Cited By ~ 4

Author(s):

Abbas Dehghani ◽

Keyvan RahimiZadeh

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Multicore Systems ◽

And Performance ◽

On Chip

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Design and Performance Evaluation of Hybrid Wired-Wireless Network on Chip Interconnect Architectures

Advances in Intelligent Systems and Computing - Third International Congress on Information and Communication Technology ◽

10.1007/978-981-13-1165-9_17 ◽

2018 ◽

pp. 191-199

Author(s):

Priyanka Mitra ◽

Bhavna Sharma ◽

Vinay Kumar Chandna ◽

Vijay Singh Rathore

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Interconnect Architectures ◽

And Performance ◽

On Chip

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A Novel Wireless Network-on-Chip Architecture for Multicore Systems

2021 26th International Computer Conference, Computer Society of Iran (CSICC) ◽

10.1109/csicc52343.2021.9420564 ◽

2021 ◽

Author(s):

Esmaeel Tahanian ◽

Mohsen Rezvani ◽

Mansoor Fateh

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Multicore Systems ◽

On Chip

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A Network on Chip Architecture and Performance Evaluation

2010 Second International Conference on Networks Security, Wireless Communications and Trusted Computing ◽

10.1109/nswctc.2010.91 ◽

2010 ◽

Cited By ~ 3

Author(s):

Wang Zhang ◽

Ligang Hou ◽

Lei Zuo ◽

Zhenyu Peng ◽

Wuchen Wu

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

And Performance ◽

On Chip

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Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

International Journal of Engineering ◽

10.5829/idosi.ije.2014.27.04a.01 ◽

2014 ◽

Vol 27 (4 (A)) ◽

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Research Note ◽

Routing Methods ◽

And Performance ◽

On Chip

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Energy and performance evaluation of a dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip architecture

2010 Annual IEEE India Conference (INDICON) ◽

10.1109/indcon.2010.5712666 ◽

2010 ◽

Cited By ~ 3

Author(s):

Kanchan Manna ◽

Santanu Chattopadhyay ◽

Indranil Sen Gupta

Keyword(s):

Performance Evaluation ◽

Routing Algorithm ◽

Network On Chip ◽

And Performance ◽

On Chip

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Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

IEEE Transactions on Computers ◽

10.1109/tc.2010.176 ◽

2011 ◽

Vol 60 (10) ◽

pp. 1485-1502 ◽

Cited By ~ 157

Author(s):

Amlan Ganguly ◽

Kevin Chang ◽

Sujay Deb ◽

Partha Pratim Pande ◽

Benjamin Belzer ◽

...

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Multicore Systems ◽

Hybrid Wireless Network ◽

On Chip

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Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746257 ◽

2008 ◽

Cited By ~ 11

Author(s):

Geng Luo-Feng ◽

Du Gao-ming ◽

Zhang Duo-Li ◽

Gao Ming-Lun ◽

Hou Ning ◽

...

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Mesh Network ◽

And Performance ◽

On Chip

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Configurable Test Environment for RTL Simulation and Performance Evaluation of Network on Chip as Part of SoC

2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) ◽

10.1109/elconrus51938.2021.9396634 ◽

2021 ◽

Author(s):

Sergey A. Chusov ◽

Evgeniy V. Primakov ◽

Yuri V. Savchenko ◽

Alexey L. Pereverzev ◽

Evgeniy S. Barkov

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Test Environment ◽

And Performance ◽

On Chip

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Towards reliability and performance-aware Wireless Network-on-Chip design

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315163 ◽

2015 ◽

Cited By ~ 2

Author(s):

Michael Opoku Agyeman ◽

Kin-Fai Tong ◽

Terrence Mak

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Chip Design ◽

And Performance ◽

On Chip

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Floorplanning exploration and performance evaluation of a new Network-on-Chip

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763103 ◽

2011 ◽

Author(s):

Licheng Xue ◽

Weixing Ji ◽

Qi Zuo ◽

Yang Zhang

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

And Performance ◽

On Chip

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