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A novel ReRAM-based processing-in-memory architecture for graph computing
2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA)
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10.1109/nvmsa.2017.8064464
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2017
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Cited By ~ 7
Author(s):
Lei Han
◽
Zhaoyan Shen
◽
Zili Shao
◽
H. Howie Huang
◽
Tao Li
Keyword(s):
Memory Architecture
◽
Graph Computing
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Cited By
References
Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules
Proceedings of the International Symposium on Memory Systems - MEMSYS '19
◽
10.1145/3357526.3357541
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2019
◽
Cited By ~ 4
Author(s):
Onkar Patil
◽
Latchesar Ionkov
◽
Jason Lee
◽
Frank Mueller
◽
Michael Lang
Keyword(s):
Memory Architecture
◽
Performance Characterization
◽
Hybrid Memory
◽
Persistent Memory
◽
Memory Modules
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Technological Design of 3D NAND based Compute-in-Memory Architecture for GB-scale Deep Neural Network
IEEE Electron Device Letters
◽
10.1109/led.2020.3048101
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2020
◽
pp. 1-1
Author(s):
Wonbo Shim
◽
Shimeng Yu
Keyword(s):
Neural Network
◽
Deep Neural Network
◽
Memory Architecture
◽
Technological Design
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TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries
Proceedings of the 2020 on Great Lakes Symposium on VLSI
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10.1145/3386263.3406896
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2020
◽
Author(s):
Sheng Xu
◽
Xiaoming Chen
◽
Xuehai Qian
◽
Yinhe Han
Keyword(s):
Memory Architecture
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CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
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10.1109/micro50266.2020.00038
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2020
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Author(s):
Dibei Chen
◽
Zhaoshi Li
◽
Tianzhu Xiong
◽
Zhiwei Liu
◽
Jun Yang
◽
...
Keyword(s):
Constant Time
◽
Memory Architecture
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Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics
2020 57th ACM/IEEE Design Automation Conference (DAC)
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10.1109/dac18072.2020.9218624
◽
2020
◽
Author(s):
Abraham Addisie
◽
Valeria Bertacco
Keyword(s):
Memory Architecture
◽
Graph Analytics
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MANNA: prototype of a distributed memory architecture with maximized sustained performance
Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing
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10.1109/empdp.1996.500600
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2002
◽
Cited By ~ 8
Author(s):
W.K. Giloi
◽
U. Bruening
◽
W. Schroeder-Preikschat
Keyword(s):
Distributed Memory
◽
Memory Architecture
◽
Sustained Performance
◽
Distributed Memory Architecture
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Parallelization Strategy for Elementary Morphological Operators on Graphs: Distance-Based Algorithms and Implementation on Multicore Shared-Memory Architecture
Journal of Mathematical Imaging and Vision
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10.1007/s10851-017-0737-1
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2017
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Vol 59
(1)
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pp. 136-160
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Cited By ~ 2
Author(s):
Imane Youkana
◽
Jean Cousty
◽
Rachida Saouli
◽
Mohamed Akil
Keyword(s):
Shared Memory
◽
Memory Architecture
◽
Morphological Operators
◽
Parallelization Strategy
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On the Statistical Memory Architecture Exploration and Optimization
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
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10.7873/date.2015.0839
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2015
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Cited By ~ 1
Author(s):
Charalampos Antoniadis
◽
Georgios Karakonstantis
◽
Nestor Evmorfopoulos
◽
Andreas Burg
◽
George Stamoulis
Keyword(s):
Memory Architecture
◽
Architecture Exploration
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Parallel implementation for HSLO(3)-FDTD with message passing interface on Distributed Memory Architecture
2006 International Conference on Computing & Informatics
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10.1109/icoci.2006.5276531
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2006
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Author(s):
Mohammad Khatim Hasan
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Mohamed Othman
◽
Jalil Md Desa
◽
Zulkifly Abbas
◽
Jumat Sulaiman
Keyword(s):
Message Passing
◽
Message Passing Interface
◽
Distributed Memory
◽
Parallel Implementation
◽
Memory Architecture
◽
Distributed Memory Architecture
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Or-parallel Prolog on a distributed memory architecture
The Journal of Logic Programming
◽
10.1016/s0743-1066(99)00064-3
◽
2000
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Vol 43
(2)
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pp. 173-186
◽
Cited By ~ 6
Author(s):
Fernando Silva
◽
Paul Watson
Keyword(s):
Distributed Memory
◽
Memory Architecture
◽
Distributed Memory Architecture
Download Full-text
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