A partitioning-free methodology for optimized gate-level monolithic 3D designs

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309221 ◽

2017 ◽

Author(s):

O. Billoint ◽

M. Brocard ◽

S. Thuries ◽

G. Berhault ◽

H. Sarhan

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