2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Latest Publications

TOTAL DOCUMENTS

101

(FIVE YEARS 0)

H-INDEX

3

(FIVE YEARS 0)

Published By IEEE

9781538637661

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Review of progress in understanding the electron transport properties of amorphous chalcogenide phase change semiconductors (Invited paper)

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308733 ◽

2017 ◽

Author(s):

Jie Liu

Keyword(s):

Electron Transport ◽

Phase Change ◽

Transport Properties ◽

Amorphous Chalcogenide ◽

Electron Transport Properties

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A 28 nW CMOS supply voltage monitor for adaptive ultra-low power IoT chips

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8344104 ◽

2017 ◽

Author(s):

Divya Akella Kamakshi ◽

Harsh N. Patel ◽

Abhishek Roy ◽

Benton H. Calhoun

Keyword(s):

Low Power ◽

Supply Voltage ◽

Ultra Low Power

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An ultra-low-power FPGA for IoT applications

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308753 ◽

2017 ◽

Author(s):

He Qi ◽

Oluseyi Ayorinde ◽

Benton H. Calhoun

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Iot Applications

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Piezoelectronic transistor for low-voltage high-speed integrated electronics

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308759 ◽

2017 ◽

Author(s):

S. Sugahara ◽

Y. Shuto ◽

S. Yamamoto ◽

H. Funakubo ◽

M. K. Kurosawa

Keyword(s):

Low Voltage ◽

Integrated Electronics

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Differential input output CMOS (DINO-CMOS) — High performance and energy efficient logic family

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309253 ◽

2017 ◽

Author(s):

M. Haber ◽

I. Levi ◽

Y. Yehoshua ◽

A. Fish

Keyword(s):

Energy Efficient ◽

High Performance ◽

Input Output ◽

Differential Input

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PVT compensation in Mie Fujitsu 55 nm DDC: A standard-cell library based comparison

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309246 ◽

2017 ◽

Author(s):

Thomas Christoph Muller ◽

Jean-Luc Nagel ◽

Marc Pons ◽

Daniel Severac ◽

Katsuhiro Hashiba ◽

...

Keyword(s):

Standard Cell ◽

Standard Cell Library ◽

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First demonstration of symmetric lateral NPN transistors on SOI featuring epitaxially-grown emitter/collector regions

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309229 ◽

2017 ◽

Author(s):

Pouya Hashemi ◽

Jeng-Bang Yau ◽

Kevin K. Chan ◽

Tak H. Ning ◽

Ghavam G. Shahidi

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Reliability analysis on low temperature gate stack process steps for 3D sequential integration

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309219 ◽

2017 ◽

Author(s):

A. Tsiara ◽

X. Garros ◽

C.-M. V. Lu ◽

C. Fenouillet-Beranger ◽

P. Batude ◽

...

Keyword(s):

Low Temperature ◽

Reliability Analysis ◽

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A partitioning-free methodology for optimized gate-level monolithic 3D designs

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309221 ◽

2017 ◽

Author(s):

O. Billoint ◽

M. Brocard ◽

S. Thuries ◽

G. Berhault ◽

H. Sarhan

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An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309224 ◽

2017 ◽

Author(s):

Yoshiki Yamamoto ◽

Takumi Hasegawa ◽

Makoto Yabuuchi ◽

Koji Nii ◽

Yohei Sawada ◽

...

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