An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309224 ◽

2017 ◽

Author(s):

Yoshiki Yamamoto ◽

Takumi Hasegawa ◽

Makoto Yabuuchi ◽

Koji Nii ◽

Yohei Sawada ◽

...

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