Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2014.2304660 ◽

2014 ◽

Vol 61 (7) ◽

pp. 2150-2158 ◽

Author(s):

Fabian Angarita ◽

Javier Valls ◽

Vicenc Almenar ◽

Vicente Torres

Keyword(s):

Error Floor ◽

Reduced Complexity

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Algebraic Quasi-Cyclic LDPC Codes: Construction, Low Error-Floor, Large Girth and a Reduced-Complexity Decoding Scheme

IEEE Transactions on Communications ◽

10.1109/tcomm.2014.2339329 ◽

2014 ◽

Vol 62 (8) ◽

pp. 2626-2637 ◽

Author(s):

Juane Li ◽

Keke Liu ◽

Shu Lin ◽

Khaled Abdel-Ghaffar

Keyword(s):

Error Floor ◽

Large Girth ◽

Reduced Complexity

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Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

IET 8th International Conference on Wireless, Mobile & Multimedia Networks ◽

10.1049/cp.2019.1150 ◽

2019 ◽

Author(s):

Hui Xue ◽

Lijun Zhang

Keyword(s):

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A Deep Learning-Aided Post-Processing Scheme to Lower the Error Floor of LDPC Codes

2020 IEEE 20th International Conference on Communication Technology (ICCT) ◽

10.1109/icct50939.2020.9295784 ◽

2020 ◽

Author(s):

Jiajun He

Keyword(s):

Deep Learning ◽

Error Floor ◽

Post Processing ◽

Processing Scheme

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Lowering the Error Floor of LDPC Codes by a Two-stage Hybrid Decoding Algorithm

2007 Second International Conference on Communications and Networking in China ◽

10.1109/chinacom.2007.4469460 ◽

2007 ◽

Author(s):

Yueguang Bian ◽

Youzheng Wang ◽

Jing Wang

Keyword(s):

Error Floor ◽

Decoding Algorithm ◽

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Structured LDPC codes for high-density recording: large girth and low error floor

IEEE Transactions on Magnetics ◽

10.1109/tmag.2005.861748 ◽

2006 ◽

Vol 42 (2) ◽

pp. 208-213 ◽

Author(s):

J. Lu ◽

J.M.F. Moura

Keyword(s):

High Density ◽

Error Floor ◽

High Density Recording ◽

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New PEG algorithm with low error floor for construction of irregular LDPC codes

2015 IEEE International Conference on Computer and Communications (ICCC) ◽

10.1109/compcomm.2015.7387584 ◽

2015 ◽

Author(s):

Feijin Shi ◽

Shuangshuang Han

Keyword(s):

Error Floor ◽

Irregular Ldpc Codes

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Quantized min-sum decoders with low error floor for LDPC codes

2012 IEEE International Symposium on Information Theory Proceedings ◽

10.1109/isit.2012.6284049 ◽

2012 ◽

Author(s):

Xiaojie Zhang ◽

Paul H. Siegel

Keyword(s):

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FPGA Implementation of Reduced Complexity LDPC Codes

DJ Journal of Advances in Electronics and Communication Engineering ◽

10.18831/djece.org/2019011001 ◽

2018 ◽

Vol 5 (1) ◽

pp. 1-9

Author(s):

N Murali Krishna ◽

Keyword(s):

Fpga Implementation ◽

Reduced Complexity

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Reduced Complexity and Improved Performance for Short Regular LDPC Codes Based on Select Updating Schedule

2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring ◽

10.1109/vetecs.2007.320 ◽

2007 ◽

Author(s):

Jianquan Liu ◽

Youyun Xu ◽

Yueming Cai

Keyword(s):

Reduced Complexity ◽

Improved Performance

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Reduced-Complexity Linear Programming Decoding Based on ADMM for LDPC Codes

IEEE Communications Letters ◽

10.1109/lcomm.2015.2418261 ◽

2015 ◽

Vol 19 (6) ◽

pp. 909-912 ◽

Author(s):

Haoyuan Wei ◽

Xiaopeng Jiao ◽

Jianjun Mu

Keyword(s):

Linear Programming ◽

Linear Programming Decoding ◽

Reduced Complexity

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