A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

1996 Symposium on VLSI Circuits. Digest of Technical Papers ◽

10.1109/vlsic.1996.507766 ◽

2002 ◽

Author(s):

H. Nakano ◽

D. Takashima ◽

K. Tsuchida ◽

S. Shiratake ◽

T. Inaba ◽

...

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