A sophisticated bit-by-bit verifying scheme for NAND EEPROMs

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215) ◽

10.1109/vlsic.1998.688098 ◽

2002 ◽

Author(s):

K. Sakui ◽

K. Kanda ◽

H. Nakamura ◽

K. Imamiya ◽

J. Miyamoto

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