An 8Mbit DRAM Design Using a 1TBulk Cell

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005. ◽

10.1109/vlsic.2005.1469404 ◽

2005 ◽

Author(s):

P. Malinge ◽

P. Candelier ◽

F. Jacquet ◽

S. Martin ◽

R. Ranica ◽

...

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