Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.
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A Six-Port 57GB/s Double-Pumped Nonblocking Router Core

2005 ◽  
Author(s):  
S. Vangal ◽  
N. Borkar ◽  
A. Alvandpour

scholarly journals A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-μm CMOS technology

2005 ◽  
Author(s):  
Jri Lee ◽  
Jian-Yu Ding ◽  
Tuan-Yi Cheng
Keyword(s):  
Cmos Technology

An 8Mbit DRAM Design Using a 1TBulk Cell

2005 ◽  
Author(s):  
P. Malinge ◽  
P. Candelier ◽  
F. Jacquet ◽  
S. Martin ◽  
R. Ranica ◽  
...  

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

2005 ◽  
Author(s):  
Jung-Hwan Choi ◽  
Young-Soo Sohn ◽  
Chan-Kyoung Kim ◽  
Won-Ki Park ◽  
Jae-Hyung Lee ◽  
...  
Keyword(s):  
Low Latency

A First RF Digitally-Controlled Oscillator for SAW-less TX in Cellular Systems

2005 ◽  
Author(s):  
Chih-Ming Hung ◽  
N. Barton ◽  
R.B. Staszewski ◽  
Meng-Chang Lee ◽  
D. Leipold
Keyword(s):  
Cellular Systems ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

2.8Gb/s Inductively Coupled Interconnect for 3-D ICs

2005 ◽  
Author(s):  
Jian Xu ◽  
J. Wilson ◽  
S. Mick ◽  
Lei Luo ◽  
P. Franzon
Keyword(s):  
Inductively Coupled
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