A 0.10-μm CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) ◽

10.1109/vlsit.1999.799363 ◽

2003 ◽

Author(s):

H. Wakabayashi ◽

T. Yamamoto ◽

Y. Saito ◽

T. Ogura ◽

M. Narihiro ◽

...

Download Full-text