Streamline verification process with formal property verification to meet highly compressed design cycle

Author(s):  
Prosenjit Chatterjee
Author(s):  
Aritra Hazra ◽  
Ansuman Banerjee ◽  
Srobona Mitra ◽  
Pallab Dasgupta ◽  
Partha Pratim Chakrabarti ◽  
...  

Author(s):  
Limor Fix ◽  
Ken McMillan ◽  
Norris Ip ◽  
Leopold Haller

Author(s):  
P. Basu ◽  
S. Das ◽  
A. Banerjee ◽  
P. Dasgupta ◽  
P.P. Chakrabarti ◽  
...  

2022 ◽  
Vol 72 (1) ◽  
pp. 40-48
Author(s):  
K.H. Kochaleema ◽  
G. Santhosh Kumar

This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML Statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation.


Author(s):  
Limor Fix ◽  
Ken McMillan ◽  
Norris Ip ◽  
Leopold Haller

2015 ◽  
pp. 87-117
Author(s):  
Erik Seligman ◽  
Tom Schubert ◽  
M V Achutha Kiran Kumar

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