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Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - PPoPP '17
◽
10.1145/3018743.3018744
◽
2017
◽
Cited By ~ 10
Author(s):
Nirmal Prajapati
◽
Waruna Ranasinghe
◽
Sanjay Rajopadhye
◽
Rumen Andonov
◽
Hristo Djidjev
◽
...
Keyword(s):
Size Selection
◽
Tile Size
◽
Time Modeling
◽
Selection For
◽
Analytical Time
Download Full-text
Related Documents
Cited By
References
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
ACM SIGPLAN Notices
◽
10.1145/3155284.3018744
◽
2017
◽
Vol 52
(8)
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pp. 163-177
◽
Cited By ~ 1
Author(s):
Nirmal Prajapati
◽
Waruna Ranasinghe
◽
Sanjay Rajopadhye
◽
Rumen Andonov
◽
Hristo Djidjev
◽
...
Keyword(s):
Size Selection
◽
Tile Size
◽
Time Modeling
◽
Selection For
◽
Analytical Time
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Impact of Tile-Size Selection for Skewed Tiling
Interaction between Compilers and Computer Architectures
◽
10.1007/978-1-4757-3337-2_3
◽
2001
◽
pp. 45-68
◽
Cited By ~ 4
Author(s):
Yonghong Song
◽
Zhiyuan Li
Keyword(s):
Size Selection
◽
Tile Size
◽
Selection For
Download Full-text
Tile size selection for optimized memory reuse in high-level synthesis
2017 27th International Conference on Field Programmable Logic and Applications (FPL)
◽
10.23919/fpl.2017.8056810
◽
2017
◽
Cited By ~ 2
Author(s):
Junyi Liu
◽
John Wickerson
◽
George A. Constantinides
Keyword(s):
High Level Synthesis
◽
Size Selection
◽
Tile Size
◽
Selection For
◽
High Level
◽
Memory Reuse
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Model-Driven Tile Size Selection for DOACROSS Loops on GPUs
Euro-Par 2011 Parallel Processing - Lecture Notes in Computer Science
◽
10.1007/978-3-642-23397-5_40
◽
2011
◽
pp. 401-412
◽
Cited By ~ 9
Author(s):
Peng Di
◽
Jingling Xue
Keyword(s):
Size Selection
◽
Model Driven
◽
Tile Size
◽
Selection For
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Tile size selection for low-power tile-based architectures
Proceedings of the 3rd conference on Computing frontiers - CF '06
◽
10.1145/1128022.1128036
◽
2006
◽
Cited By ~ 3
Author(s):
John Oliver
◽
Ravishankar Rao
◽
Michael Brown
◽
Jennifer Mankin
◽
Diana Franklin
◽
...
Keyword(s):
Low Power
◽
Size Selection
◽
Tile Size
◽
Selection For
Download Full-text
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture
Lecture Notes in Computer Science - Transactions on High-Performance Embedded Architectures and Compilers I
◽
10.1007/978-3-540-71528-3_17
◽
2007
◽
pp. 259-278
Author(s):
John Oliver
◽
Diana Franklin
◽
Frederic T. Chong
◽
Venkatesh Akella
Keyword(s):
Size Selection
◽
Tile Size
◽
Selection For
Download Full-text
Apparel Research Network (ARN) Program Size Selection for ARNSCAN
10.21236/ada385377
◽
2001
◽
Author(s):
Carol Ring
Keyword(s):
Research Network
◽
Size Selection
◽
Selection For
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A practical tile size selection model for affine loop nests
Proceedings of the ACM International Conference on Supercomputing
◽
10.1145/3447818.3462213
◽
2021
◽
Author(s):
Kumudha Narasimhan
◽
Aravind Acharya
◽
Abhinav Baid
◽
Uday Bondhugula
Keyword(s):
Selection Model
◽
Size Selection
◽
Tile Size
◽
Loop Nests
Download Full-text
Optimal size selection for fuel cell and battery in a hybrid power system of the intercity locomotives
Journal of Cleaner Production
◽
10.1016/j.jclepro.2021.128498
◽
2021
◽
pp. 128498
Author(s):
Guiju Zhang
◽
Hao Li
◽
Caiyuan Xiao
◽
Kittisak Jermsittiparsert
Keyword(s):
Fuel Cell
◽
Power System
◽
Optimal Size
◽
Hybrid Power System
◽
Size Selection
◽
Hybrid Power
◽
Selection For
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Automatic creation of tile size selection models
Proceedings of the 8th annual IEEE/ ACM international symposium on Code generation and optimization - CGO '10
◽
10.1145/1772954.1772982
◽
2010
◽
Cited By ~ 27
Author(s):
Tomofumi Yuki
◽
Lakshminarayanan Renganarayanan
◽
Sanjay Rajopadhye
◽
Charles Anderson
◽
Alexandre E. Eichenberger
◽
...
Keyword(s):
Selection Models
◽
Size Selection
◽
Tile Size
Download Full-text
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