Exact and Practical Modulo Scheduling for High-Level Synthesis

Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Andreas Koch; Oliver Sinnen

doi:10.1145/3317670

Exact and Practical Modulo Scheduling for High-Level Synthesis

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3317670 ◽

2019 ◽

Vol 12 (2) ◽

pp. 1-26 ◽

Cited By ~ 2

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Andreas Koch ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Scaling Up Modulo Scheduling for High-Level Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2018.2834440 ◽

2019 ◽

Vol 38 (5) ◽

pp. 912-925

Author(s):

Leandro de Souza Rosa ◽

Christos-Savvas Bouganis ◽

Vanderlei Bonato

Keyword(s):

Scaling Up ◽

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '17 ◽

10.1145/3020078.3021778 ◽

2017 ◽

Author(s):

Tianyi Lu ◽

Shouyi Yin ◽

Xianqing Yao ◽

Zhicong Xie ◽

Leibo Liu ◽

...

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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ILP-based modulo scheduling for high-level synthesis

Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES '16 ◽

10.1145/2968455.2968512 ◽

2016 ◽

Cited By ~ 9

Author(s):

Julian Oppermann ◽

Andreas Koch ◽

Melanie Reuter-Oppermann ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Non-iterative SDC modulo scheduling for high-level synthesis

Microprocessors and Microsystems ◽

10.1016/j.micpro.2021.104334 ◽

2021 ◽

pp. 104334

Author(s):

Leandro de Souza Rosa ◽

Christos-Savvas Bouganis ◽

Vanderlei Bonato

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis

2018 28th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2018.00055 ◽

2018 ◽

Cited By ~ 1

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Oliver Sinnen ◽

Andreas Koch

Keyword(s):

Dependence Graph ◽

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Memory fartitioning-based modulo scheduling for high-level synthesis

2017 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2017.8050969 ◽

2017 ◽

Cited By ~ 1

Author(s):

Tianyi Lu ◽

Shouyi Yin ◽

Xianqing Yao ◽

Zhicong Xie ◽

Leibo Liu ◽

...

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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