scholarly journals A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

2013 ◽  
Vol 10 (9) ◽  
pp. 20130210-20130210 ◽  
Author(s):  
Hong Liang ◽  
He Weifeng ◽  
Zhu Hui ◽  
Mao Zhigang
Keyword(s):  
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