A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard
2013 ◽
Vol 10
(9)
◽
pp. 20130210-20130210
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Keyword(s):
2009 ◽
Vol 55
(2)
◽
pp. 728-733
◽
Keyword(s):
Keyword(s):
2005 ◽
Vol 51
(4)
◽
pp. 1291-1299
◽
2006 ◽
Vol E89-A
(4)
◽
pp. 979-988
◽
Keyword(s):
Keyword(s):