Proceedings of the 20th Annual International Symposium on Computer Architecture
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Published By IEEE Comput. Soc. Press

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The Chinese Remainder Theorem And The Prime Memory System

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698573 ◽

2005 ◽

Cited By ~ 9

Author(s):

Q.S. Gao

Keyword(s):

Chinese Remainder Theorem ◽

Memory System

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Acase For Two-way Skewed-associative Caches

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698558 ◽

2005 ◽

Cited By ~ 56

Author(s):

A. Seznec

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An Adaptive Cache Coherence Protocol Optimized For Migratory Sharing

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698551 ◽

2005 ◽

Cited By ~ 13

Author(s):

P. Stenstrom ◽

M. Brorsson ◽

L. Sandberg

Keyword(s):

Cache Coherence ◽

Cache Coherence Protocol ◽

Adaptive Cache

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Mechanisms For Cooperative Shared Memory

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698554 ◽

2005 ◽

Cited By ~ 11

Author(s):

D.A. Wood ◽

S. Chandra ◽

B. Falsafi ◽

M.D. Hill ◽

J.R. Larus ◽

...

Keyword(s):

Shared Memory

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Performance Of Cached Dram Organizations In Vector Supercomputers

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698572 ◽

2005 ◽

Author(s):

W.-C. Hsul ◽

J.E. Smith

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The Architecture Of A Fault-tolerant Cached RAID Controller

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698547 ◽

2005 ◽

Cited By ~ 17

Author(s):

J. Menon ◽

J. Cortney

Keyword(s):

Fault Tolerant

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The Cedar System And An Initial Performance Study

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698562 ◽

2005 ◽

Cited By ~ 19

Author(s):

D. Kuck ◽

E. Davidson ◽

D. Lawrie ◽

A. Sameh ◽

C.-Q. Zhu ◽

...

Keyword(s):

Performance Study

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Register Connection: A New Approach To Adding Registers Into Instruction Set Architectures

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698565 ◽

2005 ◽

Cited By ~ 9

Author(s):

T. Kiyohara ◽

S. Mahlke ◽

W. Chen ◽

R. Bringmann ◽

R. Hank ◽

...

Keyword(s):

Instruction Set ◽

New Approach

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Improving AP1000 Parallel Computer Performance With Message Communication

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698571 ◽

2005 ◽

Cited By ~ 3

Author(s):

T. Horie ◽

K. Hayashi ◽

T. Shimizu ◽

H. Ishihata

Keyword(s):

Parallel Computer ◽

Computer Performance ◽

Message Communication

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Parity Logging Overcoming The Small Write Problem In Redundant Disk Arrays

Proceedings of the 20th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1993.698546 ◽

2005 ◽

Cited By ~ 17

Author(s):

D. Stodolsky ◽

G. Gibson ◽

M. Holland

Keyword(s):

Disk Arrays ◽

Redundant Disk Arrays

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Proceedings of the 20th Annual International Symposium on Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

The Chinese Remainder Theorem And The Prime Memory System

Acase For Two-way Skewed-associative Caches

An Adaptive Cache Coherence Protocol Optimized For Migratory Sharing

Mechanisms For Cooperative Shared Memory

Performance Of Cached Dram Organizations In Vector Supercomputers

The Architecture Of A Fault-tolerant Cached RAID Controller

The Cedar System And An Initial Performance Study

Register Connection: A New Approach To Adding Registers Into Instruction Set Architectures

Improving AP1000 Parallel Computer Performance With Message Communication

Parity Logging Overcoming The Small Write Problem In Redundant Disk Arrays

Proceedings of the 20th Annual International Symposium on Computer Architecture
Latest Publications