Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization
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Congestion Optimization During Interconnect Synthesis and Routing

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_4 ◽

2007 ◽

pp. 97-143

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An Introduction to Routing Congestion

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_1 ◽

2007 ◽

pp. 3-29

Keyword(s):

Routing Congestion

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Congestion Optimization During Technology Mapping and Logic Synthesis

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_6 ◽

2007 ◽

pp. 189-229

Keyword(s):

Logic Synthesis ◽

Technology Mapping

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Congestion Optimization During Placement

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_5 ◽

2007 ◽

pp. 145-188

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Placement-level Metrics for Routing Congestion

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_2 ◽

2007 ◽

pp. 33-66

Keyword(s):

Routing Congestion

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Synthesis-level Metrics for Routing Congestion

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_3 ◽

2007 ◽

pp. 67-94

Keyword(s):

Routing Congestion

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Congestion Implications of High Level Design

Series on Integrated Circuits and Systems - Routing Congestion in VLSI Circuits: Estimation and Optimization ◽

10.1007/0-387-48550-3_7 ◽

2007 ◽

pp. 231-235

Keyword(s):

Level Design ◽

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