2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
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9781467364935, 9781467364911, 9781467364928

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs)

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558412 ◽

2013 ◽

Cited By ~ 6

Author(s):

Ran Manevich ◽

Israel Cidon ◽

Avinoam Kolodny

Keyword(s):

Dynamic Traffic ◽

Hierarchical Networks ◽

Networks On Chip ◽

Traffic Distribution ◽

On Chip

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Accelerating atomic operations on GPGPUs

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558404 ◽

2013 ◽

Cited By ~ 1

Author(s):

Sean Franey ◽

Mikko Lipasti

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A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558407 ◽

2013 ◽

Cited By ~ 5

Author(s):

Jinho Lee ◽

Kiyoung Choi

Keyword(s):

Routing Algorithm ◽

Virtual Channel

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Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558401 ◽

2013 ◽

Cited By ~ 22

Author(s):

Masoumeh Ebrahimi ◽

Masoud Daneshtalab ◽

Juha Plosila ◽

Hannu Tenhunen

Keyword(s):

Fault Tolerant ◽

Minimal Path ◽

Networks On Chip ◽

Retaining Structure ◽

On Chip

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Energy-efficient adaptive wireless NoCs architecture

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558400 ◽

2013 ◽

Cited By ~ 16

Author(s):

Dominic DiTomaso ◽

Avinash Kodi ◽

David Matolak ◽

Savas Kaya ◽

Soumyasanta Laha ◽

...

Keyword(s):

Energy Efficient

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[Front cover]

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558398 ◽

2013 ◽

Keyword(s):

Front Cover

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Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558409 ◽

2013 ◽

Cited By ~ 2

Author(s):

Nithin Michael ◽

Yao Wang ◽

G. Edward Suh ◽

Ao Tang

Keyword(s):

Energy Efficient ◽

Task Mapping ◽

On Chip ◽

Many Core

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On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558418 ◽

2013 ◽

Cited By ~ 15

Author(s):

Xiaohang Wang ◽

Terrence Mak ◽

Mei Yang Yingtao Jiang ◽

Masoud Daneshtalab ◽

Maurizio Palesi

Keyword(s):

Network Flow ◽

Dynamic Network ◽

Networks On Chip ◽

Dynamic Network Flow ◽

Self Tuning ◽

On Chip

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Physical planning for the architectural exploration of large-scale chip multiprocessors

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558399 ◽

2013 ◽

Cited By ~ 1

Author(s):

Javier de San Pedro ◽

Nikita Nikitin ◽

Jordi Cortadella ◽

Jordi Petit

Keyword(s):

Large Scale ◽

Chip Multiprocessors ◽

Physical Planning ◽

Architectural Exploration

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Per-flow delay bound analysis based on a formalized microarchitectural model

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) ◽

10.1109/nocs.2013.6558411 ◽

2013 ◽

Cited By ~ 8

Author(s):

Xueqian Zhao ◽

Zhonghai Lu

Keyword(s):

Delay Bound ◽

Bound Analysis

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2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs)

Accelerating atomic operations on GPGPUs

A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip

Energy-efficient adaptive wireless NoCs architecture

[Front cover]

Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

Physical planning for the architectural exploration of large-scale chip multiprocessors

Per-flow delay bound analysis based on a formalized microarchitectural model

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
Latest Publications