Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures

Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00127 ◽

2009 ◽

Vol 31 (1) ◽

pp. 127-132

Author(s):

Zhi-Xiong ZHOU ◽

Hu HE ◽

Xu YANG ◽

Yan-Jun ZHANG ◽

Yi-He SUN

Keyword(s):

Scheduling Algorithm ◽

Instruction Scheduling ◽

Register File

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Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings. ◽

10.1109/micro.2002.1176244 ◽

2003 ◽

Cited By ~ 6

Author(s):

E. Gibert ◽

J. Sanchez ◽

A. Gonzalez

Keyword(s):

Effective Instruction ◽

Instruction Scheduling ◽

Vliw Processor

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The Marion system for retargetable instruction scheduling

Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation - PLDI '91 ◽

10.1145/113445.113465 ◽

1991 ◽

Cited By ~ 22

Author(s):

David G. Bradlee ◽

Robert R. Henry ◽

Susan J. Eggers

Keyword(s):

Instruction Scheduling

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Integrating register allocation and instruction scheduling for RISCs

ACM SIGPLAN Notices ◽

10.1145/106973.106986 ◽

1991 ◽

Vol 26 (4) ◽

pp. 122-131 ◽

Cited By ~ 3

Author(s):

David G. Bradlee ◽

Susan J. Eggers ◽

Robert R. Henry

Keyword(s):

Register Allocation ◽

Instruction Scheduling

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The Marion system for retargetable instruction scheduling

ACM SIGPLAN Notices ◽

10.1145/113446.113465 ◽

1991 ◽

Vol 26 (6) ◽

pp. 229-240 ◽

Cited By ~ 5

Author(s):

David G. Bradlee ◽

Robert R. Henry ◽

Susan J. Eggers

Keyword(s):

Instruction Scheduling

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Speculation techniques for improving load related instruction scheduling

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) ◽

10.1109/isca.1999.765938 ◽

2003 ◽

Cited By ~ 54

Author(s):

A. Yoaz ◽

M. Erez ◽

R. Ronen ◽

S. Jourdan

Keyword(s):

Instruction Scheduling

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Instruction scheduling using MAX-MIN ant system optimization

Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05 ◽

10.1145/1057661.1057674 ◽

2005 ◽

Cited By ~ 4

Author(s):

Gang Wang ◽

Wenrui Gong ◽

Ryan Kastner

Keyword(s):

System Optimization ◽

Instruction Scheduling ◽

Ant System

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Guiding instruction scheduling with synchronisation markers on a superscalar based multiprocessor

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:19941519 ◽

1994 ◽

Vol 141 (6) ◽

pp. 398

Author(s):

R.-Y. Hwang ◽

F. Lai

Keyword(s):

Instruction Scheduling

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Cited By ~ 5

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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A Ubiquitous Processor Free from Instruction Scheduling

2008 International Symposium on Communications and Information Technologies ◽

10.1109/iscit.2008.4700158 ◽

2008 ◽

Cited By ~ 2

Author(s):

Masa-aki Fukase ◽

Tomoaki Sato

Keyword(s):

Instruction Scheduling

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