Design of parallel optimization methods

Cybernetics ◽  
1988 ◽  
Vol 23 (5) ◽  
pp. 571-581 ◽  
Author(s):  
Yu. M. Ermol'ev ◽  
V. S. Mikhalevich ◽  
N. D. Cherpunoi
2014 ◽  
pp. 153-177
Author(s):  
Sima Noghanian ◽  
Abas Sabouni ◽  
Travis Desell ◽  
Ali Ashtari

2009 ◽  
Vol 25 (2) ◽  
pp. 143-150 ◽  
Author(s):  
N. Wang ◽  
C.-M. Tsai ◽  
K.-C. Cha

AbstractThis study examines the parallel computing as a means to minimize the execution time in the optimization applied to thermohydrodynamic (THD) lubrication. The objective of the optimization is to maximize the load capacity of a slider bearing with two design variables. A global optimization method, DIviding RECTangle (DIRECT) algorithm, is used. The first approach was to apply the parallel computing within the THD model in a shared-memory processing (SMP) environment to examine the parallel efficiency of fine-grain computation. Next, a distributed parallel computing in the search level was conducted by use of the standard DIRECT algorithm. Then, the algorithm is modified to provide a version suitable for effective parallel computing. In the latter coarse-grain computation the speedups obtained by the DIRECT algorithms are compared with some previous studies using other parallel optimization methods. In the fine-grain computation of the SMP machine, the communication and overhead time costs prohibit high speedup in the cases of four or more simultaneous threads. It is found that the standard DIRECT algorithm is an efficient sequential but less parallel-computing-friendly method. When the modified algorithm is used in the slider bearing optimization, a parallel efficiency of 96.3% is obtained in the 16-computing-node cluster. This study presents the modified DIRECT algorithm, an efficient parallel search method, for general engineering optimization problems.


Author(s):  
Rafael A. Trujillo Rasúa ◽  
Antonio M. Vidal ◽  
Víctor M. García

1997 ◽  
Author(s):  
J.C. Meza ◽  
C.D. Moen ◽  
T.D. Plantenga ◽  
P.A. Spence ◽  
C.H. Tong ◽  
...  

Mathematics ◽  
2020 ◽  
Vol 8 (11) ◽  
pp. 1894
Author(s):  
SangWoo An ◽  
YoungBeom Kim ◽  
Hyeokdong Kwon ◽  
Hwajeong Seo ◽  
Seog Chung Seo

With the development of information and communication technology, various types of Internet of Things (IoT) devices have widely been used for convenient services. Many users with their IoT devices request various services to servers. Thus, the amount of users’ personal information that servers need to protect has dramatically increased. To quickly and safely protect users’ personal information, it is necessary to optimize the speed of the encryption process. Since it is difficult to provide the basic services of the server while encrypting a large amount of data in the existing CPU, several parallel optimization methods using Graphics Processing Units (GPUs) have been considered. In this paper, we propose several optimization techniques using GPU for efficient implementation of lightweight block cipher algorithms on the server-side. As the target algorithm, we select high security and light weight (HIGHT), Lightweight Encryption Algorithm (LEA), and revised CHAM, which are Add-Rotate-Xor (ARX)-based block ciphers, because they are used widely on IoT devices. We utilize the features of the counter (CTR) operation mode to reduce unnecessary memory copying and operations in the GPU environment. Besides, we optimize the memory usage by making full use of GPU’s on-chip memory such as registers and shared memory and implement the core function of each target algorithm with inline PTX assembly codes for maximizing the performance. With the application of our optimization methods and handcrafted PTX codes, we achieve excellent encryption throughput of 468, 2593, and 3063 Gbps for HIGHT, LEA, and revised CHAM on RTX 2070 NVIDIA GPU, respectively. In addition, we present optimized implementations of Counter Mode Based Deterministic Random Bit Generator (CTR_DRBG), which is one of the widely used deterministic random bit generators to provide a large amount of random data to the connected IoT devices. We apply several optimization techniques for maximizing the performance of CTR_DRBG, and we achieve 52.2, 24.8, and 34.2 times of performance improvement compared with CTR_DRBG implementation on CPU-side when HIGHT-64/128, LEA-128/128, and CHAM-128/128 are used as underlying block cipher algorithm of CTR_DRBG, respectively.


2020 ◽  
Vol 29 (03n04) ◽  
pp. 2060010
Author(s):  
Štěpán Balcar ◽  
Martin Pilát

In this paper we describe a general framework for parallel optimization based on the island model of evolutionary algorithms. The framework runs a number of optimization methods in parallel with periodic communication. In this way, it essentially creates a parallel ensemble of optimization methods. At the same time, the system contains a planner that decides which of the available optimization methods should be used to solve the given optimization problem and changes the distribution of such methods during the run of the optimization. Thus, the system effectively solves the problem of online parallel portfolio selection. The proposed system is evaluated in a number of common benchmarks with various problem encodings as well as in two real-life problems — the optimization in recommender systems and the training of neural networks for the control of electric vehicle charging.


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