Fibre Optic Highway Based Distributed Control System

1993 ◽  
Vol 22 (2) ◽  
pp. 57-59
Author(s):  
S. C. Gupta ◽  
Atul Agarwal ◽  
K. N. Singh
Keyword(s):  
Control System ◽  
Distributed Control ◽  
Distributed Control System ◽  
Fibre Optic

Capture Strategy Based on a Distributed Control System for a Large-scale Space End-Effector

ROBOT ◽  
2011 ◽  
Vol 33 (4) ◽  
pp. 434-439 ◽  
Author(s):  
Dangyang JIE ◽  
Fenglei NI ◽  
Yisong TAN ◽  
Hong LIU ◽  
Hegao CAI
Keyword(s):  
Control System ◽  
Distributed Control ◽  
Large Scale ◽  
Scale Space ◽  
Distributed Control System ◽  
End Effector

scholarly journals Structure of distributed control system in Seimei telescope

2021 ◽  
pp. 1-8
Author(s):  
Ichiro Jikuya ◽  
Daichi Uchida ◽  
Masaru Kino ◽  
Mikio Kurita ◽  
Katsuhiko Yamada
Keyword(s):  
Control System ◽  
Distributed Control ◽  
Distributed Control System

Design of New Intelligent Redundant Serial Bus with Isolated Driver in the Distributed Control System

2014 ◽  
Vol 527 ◽  
pp. 242-247
Author(s):  
Ling Wang ◽  
Bo Mo ◽  
Qin Hua Li ◽  
Hong Mei
Keyword(s):  
Control System ◽  
Distributed Control ◽  
Distributed Control System ◽  
Ip Core ◽  
Redundant Data ◽  
Working Together

In the distributed control system, to make sure the running of the system bus is long-term, stable and reliable, we design a new intelligent redundant serial bus as the system bus, and it will be introduced in this article. The new intelligent redundant serial bus (IRSBUS) is able to be configured into a dual redundant synchronous bus or a quadruple redundant asynchronous bus, and its redundancy is hot redundant that means two groups of the four signals are working together. We mainly design a redundant IP core, a redundant protocol and the byte format. The IP core of IRSBUS consists of the following major modules: Intelligent Signal Router, Signal Transceiver, Lines-connecting Status Detector, Synchronous Controller (Master), Synchronous Transponder (Slave), Redundant Results Decider, Interrupt Generator, Dual-port RAMs, Control and Status Registers, Master / Slave Redundant Logical Controller. The redundant protocol and byte format provide an extremely strict timing to synchronize the master-slaves and transmit the information. We show that our design allow to compare the redundant data to arrive at the correct results. It also provides a way to regroup the remaining signal lines into a system bus when one or two of the four signal lines are broken. And then it detects the lines-connection status every 100 milliseconds.

Sign in / Sign up

Export Citation Format

Share Document