A CPS framework based perturbation constrained buffer planning approach in VLSI design

2017 ◽  
Vol 103 ◽  
pp. 3-10 ◽  
Author(s):  
Xiaodao Chen ◽  
Xiaohui Huang ◽  
Yang Xiang ◽  
Dongmei Zhang ◽  
Rajiv Ranjan ◽  
...  
Keyword(s):  
Vlsi Design ◽  
Planning Approach ◽  
Buffer Planning

VLSI design for diminished-1 multiplication of integers modulo a Fermat number

1988 ◽  
Vol 135 (3) ◽  
pp. 161 ◽  
Author(s):  
M. Benaissa ◽  
A. Pajayakrit ◽  
S.S. Dlay ◽  
A.G.J. Holt
Keyword(s):  
Vlsi Design ◽  
Fermat Number

Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing

2010 ◽  
Vol E93-A (12) ◽  
pp. 2424-2432
Author(s):  
Kokoro KATO ◽  
Masakazu ENDO ◽  
Tadao INOUE ◽  
Shigetoshi NAKATAKE ◽  
Masaki YAMABE ◽  
...  
Keyword(s):  
Vlsi Design ◽  
Design Intent

Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning

2013 ◽  
Vol E96.A (12) ◽  
pp. 2467-2474
Author(s):  
Katherine Shu-Min LI ◽  
Yingchieh HO ◽  
Liang-Bi CHEN
Keyword(s):  
Buffer Planning

Predictive Analysis in VLSI Design

2010 ◽  
Vol 4 (4) ◽  
pp. 33-39 ◽  
Author(s):  
Thomas Page ◽  
Gisli Thorsteinsson
Keyword(s):  
Vlsi Design ◽  
Predictive Analysis
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