Internet of Things for Smart Community Solutions

The term IoT (Internet of Things) constitutes the quickly developing advanced gadgets with highest computing power with in a constrained VLSI design space [...]

Design of Low Power Less Leakage Quarternary Adder Using CMOS

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

Low Power VLSI Design Techniques: A Review

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Architecture Design and VLSI Implementation of 3D Hand Gesture Recognition System

With advancements in technology, more and more research is being focused on enhancing daily life quality and convenience. Along with the increase in the development of gesture control systems, many controllers, such as the keyboard, mouse, and other devices, have been replaced with remote control products, which are gradually becoming more intuitive for users. However, vision-based hand gesture recognition systems still have many problems to overcome. Most hand detection methods adopt a skin filter or motion filter for pre-processing. However, in a noisy environment, it is not easy to correctly extract interesting objects. In this paper, a VLSI design with dual-cameras has been proposed to construct a depth map with a stereo matching algorithm and recognize hand gestures. The proposed system adopts an adaptive depth filter to separate interesting foreground objects from the background. We also propose dynamic gesture recognition using depth and coordinate information. The system can perform static and dynamic gesture recognition. The ASIC design is implemented in TSMC 90 nm with about 47.3 K gate counts, and 27.8 mW of power consumption. The average accuracy of each gesture recognition is 83.98%.