VLSI systolic arrays for band matrix multiplication

Integration ◽  
1983 ◽  
Vol 1 (2-3) ◽  
pp. 233-249 ◽  
Author(s):  
G. Alia
2011 ◽  
Vol 03 (01) ◽  
pp. 77-86
Author(s):  
DRAGAN M. RANDJELOVIĆ

The objective of this paper is to discuss systolic arrays (SAs) that are suitable for regular three-nested loop algorithms implementation and which enable the possibility of high dependability calculations for the SAs obtained in this way. This is made by considering the different possible values of flow period of processor for SAs synthesized on adaptable algorithms. Therefore, the algorithm for two matrix multiplication is one typical adaptable algorithm obtained results illustrated in the end of this paper by the examples of two rectangular matrix multiplication realized with the so called flowing and hexagonal two dimensional 2D SAs of planar SAs group.


Author(s):  
Peter Benner ◽  
Alfredo Remon ◽  
Ernesto Dufrechou ◽  
Pablo Ezzatti ◽  
Enrique S. Quintana-Orti

1997 ◽  
Vol 33 (6) ◽  
pp. 17-35 ◽  
Author(s):  
I.Z. Milentijević ◽  
I.Z̆. Milovanović ◽  
E.I. Milovanović ◽  
M.K. Stojc̆ev

1987 ◽  
Vol 4 (3) ◽  
pp. 239-258 ◽  
Author(s):  
Kam Hoi Cheng ◽  
Sartaj Sahni

2021 ◽  
Vol 15 ◽  
pp. 1-7
Author(s):  
Halil Snopce ◽  
Azir Aliu

This paper deals with the latency analysis in a twodimensional systolic array for matrix multiplication. The latency for all possible connection schemes is discussed. In this way there is obtained the lower bound of the latency that can be achieved using such arrays.


Author(s):  
Ernesto Dufrechou ◽  
Pablo Ezzatti ◽  
Enrique S. Quintana-Ortí ◽  
Alfredo Remón

Sign in / Sign up

Export Citation Format

Share Document