Parallel logic simulation with assignable delays on a vector multiprocessor computer

1997 ◽  
Vol 144 (1) ◽  
pp. 5
Author(s):  
Y.-H. Jun
Keyword(s):  
Logic Simulation ◽  
Multiprocessor Computer ◽  
Parallel Logic Simulation ◽  
Vector Multiprocessor

Parallel Logic Simulation: Myth or Reality?

Computer ◽  
2012 ◽  
Vol 45 (4) ◽  
pp. 67-73 ◽  
Author(s):  
Kai-hui Chang ◽  
Chris Browy
Keyword(s):  
Logic Simulation ◽  
Parallel Logic Simulation

scholarly journals Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation

VLSI Design ◽  
1999 ◽  
Vol 9 (3) ◽  
pp. 253-270 ◽  
Author(s):  
Hong K. Kim ◽  
Jack Jean
Keyword(s):  
Discrete Event ◽  
Parallel Simulation ◽  
Logic Simulation ◽  
Intel Paragon ◽  
Partitioning Algorithm ◽  
Partitioning Algorithms ◽  
Parallel Discrete Event ◽  
High Degree ◽  
Parallel Logic Simulation

A partitioning algorithm for parallel discrete event gate-level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases and three conflicting goals can be separately considered so to reduce computational complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency, a concurrency metric that requires neither sequential nor parallel simulation is proposed. A levelization technique is used in computing the metric so to determine gates which can be evaluated at about the same time. A parallel gate-level logic simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the performance of the iCPP algorithm. The results are compared with several other partitioning algorithms to show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

Massively Parallel Logic Simulation with GPUs

2011 ◽  
Vol 16 (3) ◽  
pp. 1-20 ◽  
Author(s):  
Yuhao Zhu ◽  
Bo Wang ◽  
Yangdong Deng
Keyword(s):  
Massively Parallel ◽  
Logic Simulation ◽  
Parallel Logic Simulation

scholarly journals Parallel Logic Simulation of VLSI Systems

1995 ◽  
Author(s):  
Roger D. Chamberlain
Keyword(s):  
Logic Simulation ◽  
Parallel Logic Simulation

A query-based parallel logic simulation algorithm

1993 ◽  
Vol 24 (2) ◽  
pp. 11-21 ◽  
Author(s):  
Tomohiro Kudoh ◽  
Tetsuro Kimura ◽  
Hideharu Amano ◽  
Takuya Terasawa
Keyword(s):  
Simulation Algorithm ◽  
Logic Simulation ◽  
Parallel Logic Simulation
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