Towards high level synthesis of mixed signal ASICs

Analogue-digital ASICs: circuit techniques, design tools and applications ◽

10.1049/pbcs003e_ch16 ◽

2011 ◽

pp. 360-375

Author(s):

Maria Martins ◽

Adolfo Garcao

Keyword(s):

High Level Synthesis ◽

Mixed Signal ◽

High Level

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Analogue high-level synthesis for mixed-signal IC realisation using an Analogue Design Synthesis Assistant (ADSA)

10.1049/ic:20000479 ◽

2000 ◽

Author(s):

R.E. Massara

Keyword(s):

High Level Synthesis ◽

Design Synthesis ◽

Mixed Signal ◽

High Level ◽

Mixed Signal Ic

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Towards a specification notation for high-level synthesis of mixed-signal and analog systems

Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation ◽

10.1109/bmas.2000.888373 ◽

2002 ◽

Author(s):

A. Doboli ◽

R. Vemuri

Keyword(s):

High Level Synthesis ◽

Mixed Signal ◽

Analog Systems ◽

High Level

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Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.818302 ◽

2003 ◽

Vol 22 (11) ◽

pp. 1504-1520 ◽

Cited By ~ 26

Author(s):

A. Doboli ◽

R. Vemuri

Keyword(s):

Behavioral Modeling ◽

High Level Synthesis ◽

Mixed Signal ◽

Signal Systems ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

High Level

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Exact and Practical Modulo Scheduling for High-Level Synthesis

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3317670 ◽

2019 ◽

Vol 12 (2) ◽

pp. 1-26 ◽

Cited By ~ 2

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Andreas Koch ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

High Level

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Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278149 ◽

2020 ◽

Author(s):

Hejie Yu ◽

Jun Cheng ◽

Xiangnan Zhang ◽

Yuzhe Gao ◽

Kuizhi Mei

Keyword(s):

Neural Network ◽

Convolutional Neural Network ◽

High Level Synthesis ◽

Verilog Hdl ◽

High Level

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