Design of variable-rate irregular LDPC codes with low error floor

IEEE International Conference on Communications, 2005. ICC 2005. 2005 ◽

10.1109/icc.2005.1494431 ◽

2005 ◽

Author(s):

L. Dinoi ◽

F. Sottile ◽

S. Benedetto

Keyword(s):

Variable Rate ◽

Error Floor ◽

Irregular Ldpc Codes

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New PEG algorithm with low error floor for construction of irregular LDPC codes

2015 IEEE International Conference on Computer and Communications (ICCC) ◽

10.1109/compcomm.2015.7387584 ◽

2015 ◽

Author(s):

Feijin Shi ◽

Shuangshuang Han

Keyword(s):

Error Floor ◽

Irregular Ldpc Codes

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Lowering Error Floor of Irregular LDPC Codes by CRC and OSD Algorithm

IEICE Transactions on Communications ◽

10.1093/ietcom/e89-b.1.1 ◽

2006 ◽

Vol E89-B (1) ◽

pp. 1-10 ◽

Author(s):

S. GOUNAI

Keyword(s):

Error Floor ◽

Irregular Ldpc Codes

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Constructing Short-Length Irregular LDPC Codes with Low Error Floor

IEEE Transactions on Communications ◽

10.1109/tcomm.2010.083110.080638 ◽

2010 ◽

Vol 58 (10) ◽

pp. 2823-2834 ◽

Author(s):

Xia Zheng ◽

Francis C. M. Lau ◽

Chi K. Tse

Keyword(s):

Short Length ◽

Error Floor ◽

Irregular Ldpc Codes

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A class of irregular ldpc codes with low error floor and low encoding complexity

IEEE Communications Letters ◽

10.1109/lcomm.2006.1633327 ◽

2006 ◽

Vol 10 (5) ◽

pp. 372-374 ◽

Author(s):

Zhiyong He ◽

P. Fortier ◽

S. Roy

Keyword(s):

Error Floor ◽

Irregular Ldpc Codes

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Design and Construction of Irregular LDPC Codes for Channels with Synchronization Errors: New Aspect of Degree Profiles

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.2020eap1004 ◽

2020 ◽

Vol E103.A (10) ◽

pp. 1237-1247

Author(s):

Ryo SHIBATA ◽

Gou HOSOYA ◽

Hiroyuki YASHIMA

Keyword(s):

Synchronization Errors ◽

Irregular Ldpc Codes ◽

Design And Construction

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Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

IET 8th International Conference on Wireless, Mobile & Multimedia Networks ◽

10.1049/cp.2019.1150 ◽

2019 ◽

Author(s):

Hui Xue ◽

Lijun Zhang

Keyword(s):

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A Deep Learning-Aided Post-Processing Scheme to Lower the Error Floor of LDPC Codes

2020 IEEE 20th International Conference on Communication Technology (ICCT) ◽

10.1109/icct50939.2020.9295784 ◽

2020 ◽

Author(s):

Jiajun He

Keyword(s):

Deep Learning ◽

Error Floor ◽

Post Processing ◽

Processing Scheme

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Optimal rate for irregular LDPC codes in binary erasure channel

2011 IEEE Information Theory Workshop ◽

10.1109/itw.2011.6089360 ◽

2011 ◽

Author(s):

H. Tavakoli ◽

M. Ahmadian Attari ◽

M. Reza Peyghami

Keyword(s):

Optimal Rate ◽

Irregular Ldpc Codes ◽

Erasure Channel ◽

Binary Erasure Channel

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Design of irregular LDPC codes for BIAWGN channels with SNR mismatch

IEEE Transactions on Communications ◽

10.1109/tcomm.2009.0901.060118 ◽

2009 ◽

Vol 57 (1) ◽

pp. 6-11 ◽

Author(s):

Hamid Saeedi ◽

Amir H. Banihashemi

Keyword(s):

Irregular Ldpc Codes

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FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i48/97269 ◽

2016 ◽

Vol 9 (48) ◽

Author(s):

Sandeep Kakde ◽

Atish Khobragade ◽

M. D. Ekbal Husain

Keyword(s):

High Throughput ◽

Fpga Implementation ◽

Irregular Ldpc Codes

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