Clock Tree construction and buffer planning in Placement

2009 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2009.5250344 ◽

2009 ◽

Author(s):

Renwei Liu ◽

Yici Cai ◽

Weixiang Shen

Keyword(s):

Tree Construction ◽

Buffer Planning

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Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

Integration ◽

10.1016/j.vlsi.2010.09.002 ◽

2011 ◽

Vol 44 (1) ◽

pp. 87-101 ◽

Author(s):

Chung-Chieh Kuo ◽

Chia-Chun Tsai ◽

Trong-Yen Lee

Keyword(s):

Pattern Matching ◽

Tree Construction ◽

X Architecture ◽

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Clock tree construction using gated clock cloning

2012 4th Asia Symposium on Quality Electronic Design (ASQED) ◽

10.1109/acqed.2012.6320475 ◽

2012 ◽

Author(s):

Wun-Han Chen ◽

Hsin-Hung Chang ◽

Jui-Hung Hung ◽

Tsai-Ming Hsieh

Keyword(s):

Tree Construction ◽

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Obstacle-aware symmetrical clock tree construction

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2017.8052973 ◽

2017 ◽

Author(s):

Meng Liu ◽

Zhiwei Zhang ◽

Wenqin Sun ◽

Donglin Wang

Keyword(s):

Tree Construction

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Zero-Skew Driven for RLC Clock Tree Construction in SoC

Third International Conference on Information Technology and Applications (ICITA'05) ◽

10.1109/icita.2005.315 ◽

2005 ◽

Author(s):

Chia-Chun Tsai ◽

Jan-Ou Wu ◽

Chung-Chieh Kuo ◽

Trong-Yen Lee ◽

Wen-Ta Lee

Keyword(s):

Tree Construction ◽

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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e91-a.1.365 ◽

2008 ◽

Vol E91-A (1) ◽

pp. 365-374 ◽

Author(s):

C.-C. TSAI ◽

J.-O. WU ◽

T.-Y. LEE

Keyword(s):

Relational Clustering ◽

Tree Construction ◽

Grey Relational ◽

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Voltage-island aware X-clock tree construction for power minimization

2011 International Conference on Computer Science and Service System (CSSS) ◽

10.1109/csss.2011.5972141 ◽

2011 ◽

Author(s):

Chia-Chun Tsai ◽

Chung-Chieh Kuo ◽

Trong-Yen Lee

Keyword(s):

Power Minimization ◽

Tree Construction

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Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) ◽

10.1109/isvlsi.2007.20 ◽

2007 ◽

Author(s):

Weixiang Shen ◽

Yici Cai ◽

Xianlong Hong ◽

Jiang Hu

Keyword(s):

Low Power ◽

Tree Construction ◽

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Activity-sensitive clock tree construction for low power

Proceedings of the International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2002.146755 ◽

2002 ◽

Author(s):

Chunhong Chen ◽

Changjun Kang ◽

M. Sarrafzadeh

Keyword(s):

Low Power ◽

Tree Construction

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X-architecture zero-skew clock tree construction with performance and DFM considerations

2010 International SoC Design Conference ◽

10.1109/socdc.2010.5682914 ◽

2010 ◽

Author(s):

Chia-Chun Tsai ◽

Chung-Chieh Kuo ◽

Feng-Tzu Hsu ◽

Lin-Jeng Gu ◽

Trong-Yen Lee

Keyword(s):

Tree Construction ◽

X Architecture ◽

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Activity-sensitive clock tree construction for low power

Proceedings of the International Symposium on Low Power Electronics and Design ◽

10.1145/566408.566481 ◽

2002 ◽

Author(s):

Chunhong Chen ◽

Changjun Kang ◽

Majid Sarrafzadeh

Keyword(s):

Low Power ◽

Tree Construction

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