clock tree Latest Research Papers

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

3C Tecnología_Glosas de innovación aplicadas a la pyme ◽

10.17993/3ctecno.2021.specialissue8.667-687 ◽

2021 ◽

pp. 667-687

Author(s):

R. Rajalakshmi ◽

S. M. Ramesh ◽

P. Sivakumar

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Charge Recycling ◽

Tree Synthesis ◽

Gated Clock

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Hybrid Multisource Clock Tree Synthesis

10.1109/icecs53924.2021.9665516 ◽

2021 ◽

Author(s):

Ang Boon Chong

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Tree Synthesis

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An OCV-Aware Clock Tree Synthesis Methodology

10.1109/iccad51958.2021.9643585 ◽

2021 ◽

Author(s):

Necati Uysal ◽

Rickard Ewetz

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Synthesis Methodology ◽

Tree Synthesis

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A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits

10.1109/iccad51958.2021.9643507 ◽

2021 ◽

Author(s):

Ching-Cheng Wang ◽

Wai-Kei Mak

Keyword(s):

Logic Circuits ◽

Flux Quantum ◽

Clock Tree

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Reconfigurable Clock Tree Design Methodology for Wide Voltage Scaling Using Custom Buffer

10.1109/asicon52560.2021.9620494 ◽

2021 ◽

Author(s):

Xuexiang Wang ◽

Yiran Sun ◽

Mingming Fang

Keyword(s):

Design Methodology ◽

Voltage Scaling ◽

Clock Tree

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Clock Tree Generation by Abutment in Synchoros VLSI Design

10.1109/norcas53631.2021.9599857 ◽

2021 ◽

Author(s):

Dimitrios Stathis ◽

Panagiotis Chaourani ◽

Syed M. A. H. Jafri ◽

Ahmed Hemani

Keyword(s):

Vlsi Design ◽

Clock Tree ◽

Tree Generation

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An Approximate Symmetry Clock Tree Design with Routing Topology Prediction

10.1109/mwscas47672.2021.9531772 ◽

2021 ◽

Author(s):

Meng Liu ◽

Zhiye Zhang ◽

Jiabao Wen ◽

Yunpeng Jia

Keyword(s):

Approximate Symmetry ◽

Clock Tree ◽

Topology Prediction

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A Comparative Study on minimum skew Clock tree distribution algorithms for high-speed Digital Integrated Circuits

Journal of Physics Conference Series ◽

10.1088/1742-6596/1916/1/012125 ◽

2021 ◽

Vol 1916 (1) ◽

pp. 012125

Author(s):

Dominic Mathew ◽

S Sophia ◽

Kiran Kumar Pasupuleti

Keyword(s):

Integrated Circuits ◽

Comparative Study ◽

High Speed ◽

Digital Integrated Circuits ◽

Clock Tree ◽

Tree Distribution ◽

Distribution Algorithms

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IR Aware Cell Placement and Clock Tree Performance Optimization in FPGA Memories

2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) ◽

10.1109/iemtronics52119.2021.9422530 ◽

2021 ◽

Author(s):

Sourabh Aditya Swarnkar ◽

Mohammad Anees ◽

Kumar Rahul ◽

Santosh Yachareni

Keyword(s):

Performance Optimization ◽

Clock Tree ◽

Cell Placement ◽

Tree Performance

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A Clock Tree Prediction and Optimization Framework using Generative Adversarial Learning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3122109 ◽

2021 ◽

pp. 1-1

Author(s):

Yi-Chen Lu ◽

Jeehyun Lee ◽

Anthony Agnesina ◽

Kambiz Samadi ◽

Sung Kyu Lim

Keyword(s):

Clock Tree ◽

Adversarial Learning ◽

Optimization Framework

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clock tree
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

Hybrid Multisource Clock Tree Synthesis

An OCV-Aware Clock Tree Synthesis Methodology

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits

Reconfigurable Clock Tree Design Methodology for Wide Voltage Scaling Using Custom Buffer

Clock Tree Generation by Abutment in Synchoros VLSI Design

An Approximate Symmetry Clock Tree Design with Routing Topology Prediction

A Comparative Study on minimum skew Clock tree distribution algorithms for high-speed Digital Integrated Circuits

IR Aware Cell Placement and Clock Tree Performance Optimization in FPGA Memories

A Clock Tree Prediction and Optimization Framework using Generative Adversarial Learning

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clock treeRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

Hybrid Multisource Clock Tree Synthesis

An OCV-Aware Clock Tree Synthesis Methodology

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits

Reconfigurable Clock Tree Design Methodology for Wide Voltage Scaling Using Custom Buffer

Clock Tree Generation by Abutment in Synchoros VLSI Design

An Approximate Symmetry Clock Tree Design with Routing Topology Prediction

A Comparative Study on minimum skew Clock tree distribution algorithms for high-speed Digital Integrated Circuits

IR Aware Cell Placement and Clock Tree Performance Optimization in FPGA Memories

A Clock Tree Prediction and Optimization Framework using Generative Adversarial Learning

clock tree
Recently Published Documents