Optimized — Block based trace cache

Author(s):  
P. Sreeram ◽  
Pradeep K. Mukherjee
Keyword(s):  
1999 ◽  
Vol 27 (2) ◽  
pp. 196-207 ◽  
Author(s):  
Bryan Black ◽  
Bohuslav Rychlik ◽  
John Paul Shen
Keyword(s):  

2007 ◽  
Vol 16 (05) ◽  
pp. 711-729 ◽  
Author(s):  
AZAM BEG ◽  
YUL CHU

Recent cache schemes, such as trace cache, (fixed-sized) block cache, and variable-sized block cache, have helped improve instruction fetch bandwidth beyond the conventional instruction caches. Trace- and block-caches function by capturing the dynamic sequence of instructions. For industry standard benchmarks (e.g., SPEC2000), performance comparison of various configurations of these caches using simulations can take days or even weeks. In this paper, we demonstrate that neural network models can be time-efficient alternatives to the simulations. The models are able to predict the multi-variate and non-linear behavior of trace- and block-caches, in terms of trace miss rate and average trace length. The models can be potentially used in compiler optimization or in pedagogical settings.


2013 ◽  
Vol 133 (10) ◽  
pp. 1976-1982 ◽  
Author(s):  
Hidetaka Watanabe ◽  
Seiichi Koakutsu ◽  
Takashi Okamoto ◽  
Hironori Hirata

2016 ◽  
Vol E99.B (12) ◽  
pp. 2550-2558
Author(s):  
Sung-Hwa LIM ◽  
Yeo-Hoon YOON ◽  
Young-Bae KO ◽  
Huhnkuk LIM

2019 ◽  
Vol 20 (4) ◽  
pp. 300-309 ◽  
Author(s):  
Yuan Gao ◽  
Ying-lan Gong ◽  
Ling Xia ◽  
Ding-chang Zheng
Keyword(s):  

2011 ◽  
Vol 58 (1) ◽  
pp. 239-266 ◽  
Author(s):  
Stefaan Mys ◽  
Jürgen Slowack ◽  
Jozef Škorupa ◽  
Nikos Deligiannis ◽  
Peter Lambert ◽  
...  

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