Digital Convergence System With High Performance But Simplified Implementation

Author(s):  
George
1999 ◽  
Vol 45 (4) ◽  
pp. 1247-1252
Author(s):  
Chae Gon Oh ◽  
Yunmo Chung ◽  
Chang Wan Hong ◽  
Sung Pyo Hong

1992 ◽  
Vol 38 (3) ◽  
pp. 734-740 ◽  
Author(s):  
A. Buttar ◽  
D. Jobling ◽  
A. Rusznyak ◽  
G. Gleim ◽  
F. Heizmann

2012 ◽  
Vol 2012 ◽  
pp. 1-10
Author(s):  
Mousumi Das ◽  
Atahar Mostafa ◽  
Khan Wahid

The current trend of digital convergence leads to the need of the video encoder/decoder (codec) that should support multiple video standards on a single platform as it is expensive to use dedicated video codec chip for each standard. The paper presents a high performance circuit shared architecture that can perform the quantization of five popular video codecs such as H.264/AVC, AVS, VC-1, MPEG-2/4, and JPEG. The proposed quantizer architecture is completely division-free as the division operation is replaced by shift and addition operations for all the standards. The design is implemented on FPGA and later synthesized in CMOS 0.18 μm technology. The results show that the proposed design satisfies the requirement of all five codecs with a maximum decoding capability of 60 fps at 187 MHz on Xilinx FPGA platform for 1080 p HD video.


1996 ◽  
Vol 42 (3) ◽  
pp. 689-695 ◽  
Author(s):  
Chae Gon Oh ◽  
Jin Goo Kim ◽  
Chang Wan Hong ◽  
Sung Pyo Hong ◽  
Yunmo Chung

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