RISC-V Based Safety System-on-Chip with Hardware Comparator

In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.

Embedded software developments in KM3NeT phase I

The KM3NeT collaboration has already produced more than one thousand acquisition boards, used for building two deep-sea neutrino detectors at the bottom of the Mediterranean Sea, with the aim of instrumenting a volume of several cubic kilometers with light sensors to detect the Cherenkov radiation produced in neutrino interactions. The so-called digital optical modules, house the PMTs and the acquisition and control electronics of the module, the central logic board, which includes a Xilinx FPGA and embedded soft processor. The present work presents the architecture and functionalities of the software embedded in the soft processor of the central logic board.

Real time emulator for parallel connected dual-PMSM sensorless control

<p>This paper presents a real-time emulator of a dual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) board for supervision and observation purposes. In order to increase the reliability of the drive, a sensorless speed control method is proposed. This method allows replacing the physical sensor while guaranteeing a satisfactory operation even in faulty conditions. The novelty of the proposed approach consists of an FPGA implementation of an emulator to control the actual system. Hence, this emulator operates in real-time with actual system control in healthy or faulty mode. It gives an observation of the speed rotation in case of fault for the sake of continuity of service. The observation of the rotor position and the speed are achieved using the dSPACE DS52030D digital platform with a digital signal processor (DSP) associated with a Xilinx FPGA.</p>

A Lightweight Pedestrian Detection Engine with Two-Stage Low-Complexity Detection Network and Adaptive Region Focusing Technique

Pedestrian detection has been widely used in applications such as video surveillance and intelligent robots. Recently, deep learning-based pedestrian detection engines have attracted lots of attention. However, the computational complexity of these engines is high, which makes them unsuitable for hardware- and power-constrained mobile applications, such as drones for surveillance. In this paper, we propose a lightweight pedestrian detection engine with a two-stage low-complexity detection network and adaptive region focusing technique, to reduce the computational complexity in pedestrian detection, while maintaining sufficient detection accuracy. The proposed pedestrian detection engine has significantly reduced the number of parameters (0.73 M) and operations (1.04 B), while achieving a comparable precision (85.18%) and miss rate (25.16%) to many existing designs. Moreover, the proposed engine, together with YOLOv3 and YOLOv3-Tiny, has been implemented on a Xilinx FPGA Zynq7020 for comparison. It is able to achieve 16.3 Fps while consuming 0.59 W, which outperforms the results of YOLOv3 (5.3 Fps, 2.43 W) and YOLOv3-Tiny (12.8 Fps, 0.95 W).

Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification

This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.

Compact FPGA Ring Oscillator Physical Unclonable Functions Circuits Based on Intertwined Programmable Delay Paths

Compact FPGA based PUF extraction circuits based on intertwined programmable delay paths implemented on Xilinx FPGA.

Low latency Montgomery multiplier for cryptographic applications

In this modern era, data protection is very important. To achieve this, the data must be secured using either public-key or private-key cryptography (PKC). PKC eliminates the need of sharing key at the beginning of communication. PKC systems such as ECC and RSA is implemented for different security services such as key exchange between sender, receiver and key distribution between different network nodes and authentication protocols. PKC is based on computationally intensive finite field arithmetic operations. In the PKC schemes, modular multiplication (MM) is the most critical operation. Usually, this operation is performed by integer multiplication (IM) followed by a reduction modulo M. However, the reduction step involves a long division operation that is expensive in terms of area, time and resources. Montgomery multiplication algorithm facilitates faster MM operation without the division operation. In this paper, low latency hardware implementation of the Montgomery multiplier is proposed. Many interesting and novel optimization strategies are adopted in the proposed design. The proposed Montgomery multiplier is based on school-book multiplier, Karatsuba-Ofman algorithm and fast adders techniques. The Karatsuba-Ofman algorithm and school-book multiplier recommends cutting down the operands into smaller chunks while adders facilitate fast addition for large size operands. The proposed design is simulated, synthesized and implemented using Xilinx ISE Design Suite by targeting different Xilinx FPGA devices for different bit sizes (64-1024). The proposed design is evaluated on the basis of computational time, area consumption, and throughput. The implementation results show that the proposed design can easily outperform the state of the art

A Composable Monitoring System for Heterogeneous Embedded Platforms

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

Implementation of the visual data processing algorithms for onboard computing units

According to the short analysis of modern experience of hardware and software for autonomous mobile robots a role of computer vision systems in the structure of those robots is considered. A number of configurations of onboard computers and implementation of algorithms for visual data capturing and processing are described. In original configuration space the «algorithms-hardware» plane is considered. For software designing the realtime vision system framework is used. Experiments with the computing module based on the Intel/Altera Cyclone IV FPGA (implementation of the histogram computation algorithm and the Canny's algorithm), with the computing module based on the Xilinx FPGA (implementation of a sparse and dense optical flow algorithms) are described. Also implementation of algorithm of graph segmentation of grayscale images is considered and analyzed. Results of the first experiments are presented.

Development and implementation of the method for high resolution object tracking in 3D space

The means to track objects in 3D space is paramount to computer vision and robotics. Improving upon prior work of the M.A.R.S. project enabled more accurate object tracking and ranging, required investigation into current techniques of stereo depth estimation, object tracking algorithms and the use of FPGA platforms. The research focused on aviation, ground vehicle and robotic applications of stereo computer vision and image processing methods. The implementation of the project design focused on how to obtain greater disparity resolution from the stereo system while minimizing memory resources. The analysis of the optimal method and then the coding and debugging of the optimal solution was performed to insure inter-operability with the existing system and lay the foundation for further expansion of the system. Comparative analysis of Xilinx FPGA platforms and MATLAB simulation of the concept provided data on hardware resources, improved disparity output and the minimal use of memory.