Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics

2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL) ◽

10.1109/ismvl49045.2020.00-31 ◽

2020 ◽

Author(s):

Akira Ito ◽

Rei Ueno ◽

Naofumi Homma

Keyword(s):

Formal Verification ◽

Galois Field ◽

Arithmetic Circuits

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Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3059924 ◽

2021 ◽

pp. 1-1

Author(s):

Akira Ito ◽

Rei Ueno ◽

Naofumi Homma

Keyword(s):

Formal Verification ◽

Galois Field ◽

Arithmetic Circuits

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Formal Verification of Sequential Galois Field Arithmetic Circuits Using Algebraic Geometry

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0158 ◽

2015 ◽

Author(s):

Xiaojun Sun ◽

Priyank Kalla ◽

Tim Pruss ◽

Florian Enescu

Keyword(s):

Algebraic Geometry ◽

Formal Verification ◽

Galois Field ◽

Arithmetic Circuits

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Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2013.2259540 ◽

2013 ◽

Vol 32 (9) ◽

pp. 1409-1420 ◽

Author(s):

Jinpeng Lv ◽

Priyank Kalla ◽

Florian Enescu

Keyword(s):

Formal Verification ◽

Gröbner Basis ◽

Galois Field ◽

Arithmetic Circuits ◽

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Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases

Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14 ◽

10.1145/2593069.2593134 ◽

2014 ◽

Author(s):

Tim Pruss ◽

Priyank Kalla ◽

Florian Enescu

Keyword(s):

Gröbner Bases ◽

Galois Field ◽

Grobner Bases ◽

Arithmetic Circuits ◽

Equivalence Verification

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Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi49217.2020.00077 ◽

2020 ◽

Author(s):

Tiankai Su ◽

Atif Yasin ◽

Sebastien Pillement ◽

Maciej Ciesielski

Keyword(s):

Formal Verification ◽

Algebraic Approach ◽

Arithmetic Circuits

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A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) ◽

10.1109/ismvl.2017.35 ◽

2017 ◽

Author(s):

Rei Ueno ◽

Naofumi Homma ◽

Takafumi Aoki

Keyword(s):

Galois Field ◽

Arithmetic Circuits ◽

Systematic Design

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Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.102 ◽

2012 ◽

Author(s):

Jinpeng Lv ◽

Priyank Kalla

Keyword(s):

Formal Verification ◽

Computer Algebra ◽

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Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2018.2808457 ◽

2019 ◽

Vol 38 (2) ◽

pp. 354-365 ◽

Author(s):

Cunxi Yu ◽

Maciej Ciesielski

Keyword(s):

Reverse Engineering ◽

Formal Analysis ◽

Galois Field ◽

Arithmetic Circuits ◽

Parallel Verification

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Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Microprocessors and Microsystems ◽

10.1016/j.micpro.2015.01.007 ◽

2015 ◽

Vol 39 (2) ◽

pp. 83-96 ◽

Author(s):

Farimah Farahmandi ◽

Bijan Alizadeh

Keyword(s):

Formal Verification ◽

Gaussian Elimination ◽

Arithmetic Circuits ◽

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Efficient Gröbner basis reductions for formal verification of galois field multipliers

2011 Design, Automation & Test in Europe ◽

10.1109/date.2012.6176625 ◽

2012 ◽

Author(s):

Jinpeng Lv ◽

P. Kalla ◽

F. Enescu

Keyword(s):

Formal Verification ◽

Galois Field ◽

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