Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis

2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) ◽

10.1109/ispacs48206.2019.8986365 ◽

2019 ◽

Author(s):

Kosuke Fukava ◽

Kaito Mori ◽

Kousuke Imamura ◽

Yoshio Matsuda ◽

Tetsuya Matsumura ◽

...

Keyword(s):

High Level Synthesis ◽

Low Latency ◽

Video Encoder ◽

Design And Implementation ◽

High Level

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Design and implementation of a TV ghost cancelling system using high level synthesis tools

11th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.02CH37379) ◽

10.1109/melecon.2002.1014606 ◽

2003 ◽

Author(s):

M.S. Mousa ◽

K.T. Ibrahim ◽

A.H. Khalil ◽

A.E. Salama

Keyword(s):

High Level Synthesis ◽

Design And Implementation ◽

High Level

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Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351332 ◽

2018 ◽

Cited By ~ 1

Author(s):

Imad Benacer ◽

Francois-Raymond Boyer ◽

Yvon Savaria

Keyword(s):

High Level Synthesis ◽

Low Latency ◽

Traffic Manager ◽

High Level

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A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis

2018 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID) ◽

10.1109/ccgrid.2018.00067 ◽

2018 ◽

Cited By ~ 1

Author(s):

Thibaut Stimpfling ◽

J.M. Pierre Langlois ◽

Normand Belanger ◽

Yvon Savaria

Keyword(s):

High Level Synthesis ◽

Low Latency ◽

High Level ◽

Memory Efficient

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High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing

Integration ◽

10.1016/j.vlsi.2021.08.011 ◽

2021 ◽

Author(s):

Samuel Sirois ◽

Messaoud Ahmed Ouameur ◽

Daniel Massicotte

Keyword(s):

Massive Mimo ◽

Matrix Inversion ◽

High Level Synthesis ◽

Low Latency ◽

High Level

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P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '18 ◽

10.1145/3174243.3174270 ◽

2018 ◽

Cited By ~ 5

Author(s):

Jeferson Santiago da Silva ◽

François-Raymond Boyer ◽

J.M. Pierre Langlois

Keyword(s):

High Level Synthesis ◽

Low Latency ◽

High Level

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VLSI design and implementation of a discrete cosine transform chip for video compression using high level synthesis tools

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1994.519192 ◽

2002 ◽

Author(s):

N. Subramani ◽

T. Ogunfunmi

Keyword(s):

Discrete Cosine Transform ◽

Video Compression ◽

Vlsi Design ◽

High Level Synthesis ◽

Cosine Transform ◽

Design And Implementation ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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