Architecture for Dual-Mode Quadruple Precision Floating Point Adder

2015 ◽  
Author(s):  
Manish Kumar Jaiswal ◽  
B. Sharat Chandra Varma ◽  
Hayden K. H. So
Keyword(s):  
Floating Point ◽  
Dual Mode ◽  
Quadruple Precision

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

2018 ◽  
Vol 38 (1) ◽  
pp. 173-190 ◽  
Author(s):  
K. Thiruvenkadam ◽  
J. Ramesh ◽  
Anjali S. Pillai
Keyword(s):  
Floating Point ◽  
Dual Mode ◽  
Area Efficient

Dual-mode floating-point multiplier architectures with parallel operations

2006 ◽  
Vol 52 (10) ◽  
pp. 549-562 ◽  
Author(s):  
Ahmet Akkaş ◽  
Michael J. Schulte
Keyword(s):  
Floating Point ◽  
Dual Mode
Sign in / Sign up

Export Citation Format

Share Document