Elementary Algebra on Vedic Mathematics

The South Asian region has a long history of discovering new ideas, ideologies, and technologies. Since the Vedic period, the land has been known as a fertile place for innovative discoveries. The Vedic technique used by Bharati Krishna Tirthaji is unique among South Asian studies. The focus of this study was mostly on algebraic topics, which are typically taught in our school level. The study also looked at how Vedic Mathematics solves issues of elementary algebra using Vedic techniques such as Paravartya Yojayet, Sunyam Samyasamuccaye, Anurupye Sunyamanyat, Antyayoreva and Lopanasthapanabhyam. The comparison and discussion of the Vedic with the conventional techniques indicate that the Vedic Mathematics and its five unique formulas are more beneficial and realistic to those learners who are experiencing problems with elementary level algebra utilizing conventional methods.

VLSI Design Based Delay and Power Performance Comparison and Analysis of Multipliers

Recently, the problem of power dissipation has become more important in VLSI design. The multiplier is a major drain on resources. The multiplier is a basic operation in arithmetic. This article examines a variety of multipliers at the algorithmic, circuit, and layout levels. The multiplier schematic was designed using TANNER TOOL. It has been possible to increase the speed and area of multipliers by utilising Vedic mathematics for multiplication. Vedic mathematics' "Ni khilam sutra" formula can multiply large numbers. One of the primary objectives is to increase speed while simultaneously decreasing power, area, and delay.

A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.